High-speed and high-coding-rate Viterbi decoder VLSI - design and performance of NUFEC

Shuji Kubota, Shuzo Kato, Tsunehachi Ishitani, Mitsuyoshi Nagatani

Research output: Contribution to conferencePaperpeer-review


Summary form only given, as follows. New universal forward-error-correction (NUFEC) systems which employ the universal-coding-rate convolutional encoder and Viterbi decoder VLSIs are presented. For hardware size and power consumption reduction, two kinds of Viterbi decoder VLSIs (NUFEC type 1 and type 2) have been developed by employing CMOS 1.5-μm full-custom VLSI technology coupled with both advanced hierarchical macrocell-design and standard-cell-design techniques. The NUFEC type 1 LSI is composed of a branch metric calculator, a speed converter and a conventional R = 1/2 Viterbi decoder. It operates as a one-chip R = 1/2 Viterbi decoder with a constraint length of K = 7 by itself. The NUFEC type 2 LSI is path memory circuit for coding-rate mode > 1/2. The developed NUFEC LSIs operate up to 25 Mb/s information bit rate and are easily applicable to various higher-coding-rate convolutional codes by changing branch metric ROM tables. With this LSI implementation, the proposed NUFEC systems, which have net coding gain of 4.5 dB and 2.8 dB at Pe = 1 × 10-4 in R = 1/2 and 7/8 modes respectively, are widely usable as powerful and cost-effective general-purpose forward error-correcting systems.

Original languageEnglish
Number of pages1
Publication statusPublished - 1988 Dec 1

ASJC Scopus subject areas

  • Engineering(all)


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