Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond

T. Usami; T. Ide; Y. Kakuhara; Y. Ajima; K. Ueno; T. Maruyama; Y. Yu; E. Apen; K. Chattopadhyay; B. Van Schravendijk; N. Oda; M. Sekine

doi:10.1109/IITC.2006.1648665

Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond

T. Usami, T. Ide, Y. Kakuhara, Y. Ajima, K. Ueno, T. Maruyama, Y. Yu, E. Apen, K. Chattopadhyay, B. Van Schravendijk, N. Oda, M. Sekine

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

20 Citations (Scopus)

Abstract

A highly reliable interface using a self-aligned CuSiN process with Low-k SiC barrier dielectric (k=3.5) has been developed for 65mn node and beyond. Using this process as the barrier dielectric, a 4% reduction of the capacitance between the adjacent lines was obtained in comparison to SiCN dielectric (k=4.9) without the electrical failure in addition, 39× via electro-migration (EM) improvement and 1.5× better TZDM were obtained in companson to the baseline NH3 plasma pretreatment process. And these interfaces were analyzed by XPS, TBM-EELS. According to these analyses, the mechanism for performance enhancement is proposed.

Original language	English
Title of host publication	2006 International Interconnect Technology Conference, IITC
Pages	125-127
Number of pages	3
DOIs	https://doi.org/10.1109/IITC.2006.1648665
Publication status	Published - 2006
Externally published	Yes
Event	2006 International Interconnect Technology Conference, IITC - Burlingame, CA, United States Duration: 2006 Jun 5 → 2006 Jun 7

Publication series

Name	2006 International Interconnect Technology Conference, IITC

Conference

Conference	2006 International Interconnect Technology Conference, IITC
Country/Territory	United States
City	Burlingame, CA
Period	06/6/5 → 06/6/7

ASJC Scopus subject areas

Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/IITC.2006.1648665

Cite this

Usami, T., Ide, T., Kakuhara, Y., Ajima, Y., Ueno, K., Maruyama, T., Yu, Y., Apen, E., Chattopadhyay, K., Van Schravendijk, B., Oda, N., & Sekine, M. (2006). Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond. In 2006 International Interconnect Technology Conference, IITC (pp. 125-127). [1648665] (2006 International Interconnect Technology Conference, IITC). https://doi.org/10.1109/IITC.2006.1648665

Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond. / Usami, T.; Ide, T.; Kakuhara, Y. et al.

2006 International Interconnect Technology Conference, IITC. 2006. p. 125-127 1648665 (2006 International Interconnect Technology Conference, IITC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Usami, T, Ide, T, Kakuhara, Y, Ajima, Y, Ueno, K, Maruyama, T, Yu, Y, Apen, E, Chattopadhyay, K, Van Schravendijk, B, Oda, N & Sekine, M 2006, Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond. in 2006 International Interconnect Technology Conference, IITC., 1648665, 2006 International Interconnect Technology Conference, IITC, pp. 125-127, 2006 International Interconnect Technology Conference, IITC, Burlingame, CA, United States, 06/6/5. https://doi.org/10.1109/IITC.2006.1648665

Usami T, Ide T, Kakuhara Y, Ajima Y, Ueno K, Maruyama T et al. Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond. In 2006 International Interconnect Technology Conference, IITC. 2006. p. 125-127. 1648665. (2006 International Interconnect Technology Conference, IITC). doi: 10.1109/IITC.2006.1648665

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title = "Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond",

abstract = "A highly reliable interface using a self-aligned CuSiN process with Low-k SiC barrier dielectric (k=3.5) has been developed for 65mn node and beyond. Using this process as the barrier dielectric, a 4% reduction of the capacitance between the adjacent lines was obtained in comparison to SiCN dielectric (k=4.9) without the electrical failure in addition, 39× via electro-migration (EM) improvement and 1.5× better TZDM were obtained in companson to the baseline NH3 plasma pretreatment process. And these interfaces were analyzed by XPS, TBM-EELS. According to these analyses, the mechanism for performance enhancement is proposed.",

author = "T. Usami and T. Ide and Y. Kakuhara and Y. Ajima and K. Ueno and T. Maruyama and Y. Yu and E. Apen and K. Chattopadhyay and {Van Schravendijk}, B. and N. Oda and M. Sekine",

note = "Funding Information: We would like to dedicate this article to Professor Francesco Calogero in his 70th anniversary. This work was partially supported by the DGI under grant no. BFM2002–02646. A.E. acknowledges the financial support of the Spanish MEC through an FPU scholarship.; 2006 International Interconnect Technology Conference, IITC ; Conference date: 05-06-2006 Through 07-06-2006",

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doi = "10.1109/IITC.2006.1648665",

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AU - Usami, T.

AU - Ide, T.

AU - Kakuhara, Y.

AU - Ajima, Y.

AU - Ueno, K.

AU - Maruyama, T.

AU - Yu, Y.

AU - Apen, E.

AU - Chattopadhyay, K.

AU - Van Schravendijk, B.

AU - Oda, N.

AU - Sekine, M.

N1 - Funding Information: We would like to dedicate this article to Professor Francesco Calogero in his 70th anniversary. This work was partially supported by the DGI under grant no. BFM2002–02646. A.E. acknowledges the financial support of the Spanish MEC through an FPU scholarship.

PY - 2006

Y1 - 2006

N2 - A highly reliable interface using a self-aligned CuSiN process with Low-k SiC barrier dielectric (k=3.5) has been developed for 65mn node and beyond. Using this process as the barrier dielectric, a 4% reduction of the capacitance between the adjacent lines was obtained in comparison to SiCN dielectric (k=4.9) without the electrical failure in addition, 39× via electro-migration (EM) improvement and 1.5× better TZDM were obtained in companson to the baseline NH3 plasma pretreatment process. And these interfaces were analyzed by XPS, TBM-EELS. According to these analyses, the mechanism for performance enhancement is proposed.

AB - A highly reliable interface using a self-aligned CuSiN process with Low-k SiC barrier dielectric (k=3.5) has been developed for 65mn node and beyond. Using this process as the barrier dielectric, a 4% reduction of the capacitance between the adjacent lines was obtained in comparison to SiCN dielectric (k=4.9) without the electrical failure in addition, 39× via electro-migration (EM) improvement and 1.5× better TZDM were obtained in companson to the baseline NH3 plasma pretreatment process. And these interfaces were analyzed by XPS, TBM-EELS. According to these analyses, the mechanism for performance enhancement is proposed.

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Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond

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Conference

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