Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond

T. Usami, T. Ide, Y. Kakuhara, Y. Ajima, K. Ueno, T. Maruyama, Y. Yu, E. Apen, K. Chattopadhyay, B. Van Schravendijk, N. Oda, M. Sekine

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Citations (Scopus)

Abstract

A highly reliable interface using a self-aligned CuSiN process with Low-k SiC barrier dielectric (k=3.5) has been developed for 65mn node and beyond. Using this process as the barrier dielectric, a 4% reduction of the capacitance between the adjacent lines was obtained in comparison to SiCN dielectric (k=4.9) without the electrical failure in addition, 39× via electro-migration (EM) improvement and 1.5× better TZDM were obtained in companson to the baseline NH3 plasma pretreatment process. And these interfaces were analyzed by XPS, TBM-EELS. According to these analyses, the mechanism for performance enhancement is proposed.

Original languageEnglish
Title of host publication2006 International Interconnect Technology Conference, IITC
Pages125-127
Number of pages3
DOIs
Publication statusPublished - 2006
Externally publishedYes
Event2006 International Interconnect Technology Conference, IITC - Burlingame, CA
Duration: 2006 Jun 52006 Jun 7

Other

Other2006 International Interconnect Technology Conference, IITC
CityBurlingame, CA
Period06/6/506/6/7

Fingerprint

Electromigration
Electron energy loss spectroscopy
Capacitance
X ray photoelectron spectroscopy
Plasmas

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Usami, T., Ide, T., Kakuhara, Y., Ajima, Y., Ueno, K., Maruyama, T., ... Sekine, M. (2006). Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond. In 2006 International Interconnect Technology Conference, IITC (pp. 125-127). [1648665] https://doi.org/10.1109/IITC.2006.1648665

Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond. / Usami, T.; Ide, T.; Kakuhara, Y.; Ajima, Y.; Ueno, K.; Maruyama, T.; Yu, Y.; Apen, E.; Chattopadhyay, K.; Van Schravendijk, B.; Oda, N.; Sekine, M.

2006 International Interconnect Technology Conference, IITC. 2006. p. 125-127 1648665.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Usami, T, Ide, T, Kakuhara, Y, Ajima, Y, Ueno, K, Maruyama, T, Yu, Y, Apen, E, Chattopadhyay, K, Van Schravendijk, B, Oda, N & Sekine, M 2006, Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond. in 2006 International Interconnect Technology Conference, IITC., 1648665, pp. 125-127, 2006 International Interconnect Technology Conference, IITC, Burlingame, CA, 06/6/5. https://doi.org/10.1109/IITC.2006.1648665
Usami T, Ide T, Kakuhara Y, Ajima Y, Ueno K, Maruyama T et al. Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond. In 2006 International Interconnect Technology Conference, IITC. 2006. p. 125-127. 1648665 https://doi.org/10.1109/IITC.2006.1648665
Usami, T. ; Ide, T. ; Kakuhara, Y. ; Ajima, Y. ; Ueno, K. ; Maruyama, T. ; Yu, Y. ; Apen, E. ; Chattopadhyay, K. ; Van Schravendijk, B. ; Oda, N. ; Sekine, M. / Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond. 2006 International Interconnect Technology Conference, IITC. 2006. pp. 125-127
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