Highly Reliable Interface of Self-Aligned CuSiN Process with Low-k SiC Barrier Dielectric (k=3.5) for 65nm Node and Beyond

T. Usami, T. Ide, Y. Kakuhara, Y. Ajima, K. Ueno, T. Maruyama, Y. Yu, E Apen, K. Chattopadhyay, B. van Schravendijk, N. Oda, M. Sekine

Research output: Contribution to journalArticle

20 Citations (Scopus)
Original languageEnglish
Pages (from-to)125-127
JournalProc. 2006 Int. Interconnect Tech. Conf.
Publication statusPublished - 2006 Jun 6

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Usami, T., Ide, T., Kakuhara, Y., Ajima, Y., Ueno, K., Maruyama, T., Yu, Y., Apen, E., Chattopadhyay, K., Schravendijk, B. V., Oda, N., & Sekine, M. (2006). Highly Reliable Interface of Self-Aligned CuSiN Process with Low-k SiC Barrier Dielectric (k=3.5) for 65nm Node and Beyond. Proc. 2006 Int. Interconnect Tech. Conf., 125-127.