Highly Reliable Interface of Self-Aligned CuSiN Process with Low-k SiC Barrier Dielectric (k=3.5) for 65nm Node and Beyond

T. Usami, T. Ide, Y. Kakuhara, Y. Ajima, K. Ueno, T. Maruyama, Y. Yu, E Apen, K. Chattopadhyay, B. van Schravendijk, N. Oda, M. Sekine

Research output: Contribution to journalArticle

20 Citations (Scopus)
Original languageEnglish
Pages (from-to)125-127
JournalProc. 2006 Int. Interconnect Tech. Conf.
Publication statusPublished - 2006 Jun 6

Cite this

Highly Reliable Interface of Self-Aligned CuSiN Process with Low-k SiC Barrier Dielectric (k=3.5) for 65nm Node and Beyond. / Usami, T.; Ide, T.; Kakuhara, Y.; Ajima, Y.; Ueno, K.; Maruyama, T.; Yu, Y.; Apen, E; Chattopadhyay, K.; Schravendijk, B. van; Oda, N.; Sekine, M.

In: Proc. 2006 Int. Interconnect Tech. Conf., 06.06.2006, p. 125-127.

Research output: Contribution to journalArticle

Usami, T, Ide, T, Kakuhara, Y, Ajima, Y, Ueno, K, Maruyama, T, Yu, Y, Apen, E, Chattopadhyay, K, Schravendijk, BV, Oda, N & Sekine, M 2006, 'Highly Reliable Interface of Self-Aligned CuSiN Process with Low-k SiC Barrier Dielectric (k=3.5) for 65nm Node and Beyond', Proc. 2006 Int. Interconnect Tech. Conf., pp. 125-127.
Usami, T. ; Ide, T. ; Kakuhara, Y. ; Ajima, Y. ; Ueno, K. ; Maruyama, T. ; Yu, Y. ; Apen, E ; Chattopadhyay, K. ; Schravendijk, B. van ; Oda, N. ; Sekine, M. / Highly Reliable Interface of Self-Aligned CuSiN Process with Low-k SiC Barrier Dielectric (k=3.5) for 65nm Node and Beyond. In: Proc. 2006 Int. Interconnect Tech. Conf. 2006 ; pp. 125-127.
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AU - Ueno, K.

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AU - Sekine, M.

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