Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

Toshiaki Shirai, Kimiyoshi Usami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Increase in leakage power and Vth variation is a critical concern in leading-edge CMOS technology. Traditional dual Vth design with the worst corner model becomes difficult to achieve for low leakage because delay variation of high Vth cell is increased significantly by Vth variation. In this paper, we demonstrated that a power gated cell is more tolerant in delay variation than high Vth cell in 45nm technology. We propose hybrid design technique to use power gated cells in the dual Vth circuit to reduce standby leakage without causing performance degradation. Also, we developed an optimization methodology based on simulated annealing. The proposed technique was applied to ISCAS'85 benchmark circuits. Standby leakage power was reduced by 44% on average over the conventional dual Vth design.

Original languageEnglish
Title of host publication2008 International SoC Design Conference, ISOCC 2008
Volume1
DOIs
Publication statusPublished - 2008
Event2008 International SoC Design Conference, ISOCC 2008 - Busan
Duration: 2008 Nov 242008 Nov 25

Other

Other2008 International SoC Design Conference, ISOCC 2008
CityBusan
Period08/11/2408/11/25

Fingerprint

Networks (circuits)
Simulated annealing
Degradation

Keywords

  • Dual Vth
  • Leakage current
  • Low power
  • MTCMOS
  • Power gating
  • Vth variation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

Cite this

Shirai, T., & Usami, K. (2008). Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations. In 2008 International SoC Design Conference, ISOCC 2008 (Vol. 1). [4815634] https://doi.org/10.1109/SOCDC.2008.4815634

Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations. / Shirai, Toshiaki; Usami, Kimiyoshi.

2008 International SoC Design Conference, ISOCC 2008. Vol. 1 2008. 4815634.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shirai, T & Usami, K 2008, Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations. in 2008 International SoC Design Conference, ISOCC 2008. vol. 1, 4815634, 2008 International SoC Design Conference, ISOCC 2008, Busan, 08/11/24. https://doi.org/10.1109/SOCDC.2008.4815634
Shirai, Toshiaki ; Usami, Kimiyoshi. / Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations. 2008 International SoC Design Conference, ISOCC 2008. Vol. 1 2008.
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