Implementation and evaluation of fine-grain run-time power gating for a multiplier

Kimiyoshi Usami, Mitsutaka Nakata, Toshiaki Shirai, Seidai Takeda, Naomi Seki, Hideharu Amano, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

In a 32bx32b multiplier, when the bit width of both operands is less than 16-bit, the upper array of the multiplier computing the upper bits of the product does not need to operate and hence consumes wasteful leakage energy. We propose a technique to control run-time power gating (RTPG) for the upper array by dynamically detecting the operand width. Since RTPG suffers from energy overhead due to turning on/off power switches, the sleep time at each sleep event should be longer than the break-even time (BET) to gain in energy savings. Using an analytical model we built, we show that BET reduces exponentially with higher temperature. Since the chip temperature goes up during the operation, the sleep time becomes more likely to exceed the shortened BET, leading to the increase of energy savings. We evaluated our technique through designing a 32bx32b multiplier and implementing in a commercial 90nm CMOS technology. Post-layout simulation results showed that BET reduces from 32 cycles at 25°C to 10 cycles at 65°C and to 3 cycles at 100°C at 100MHz. We also simulated energy dissipation by incorporating our multiplier into a MIPS R3000 based CPU and running a JPEG encoding program. Results showed that our technique reduces energy by 5% at 65°C and by 39% at 100°C over the PG-disabled case even counting the overhead. In contrast, energy was increased by 36% at 25°C. The ground bounce at the wakeup was effectively suppressed to 91mV by using delay-skewed buffering for power switches, while achieving the wakeup time of 1.44ns.

Original languageEnglish
Title of host publication2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
Pages7-10
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 - Austin, TX
Duration: 2009 May 182009 May 20

Other

Other2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
CityAustin, TX
Period09/5/1809/5/20

Fingerprint

Energy conservation
Switches
Program processors
Analytical models
Energy dissipation
Temperature
Sleep

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H., & Nakamura, H. (2009). Implementation and evaluation of fine-grain run-time power gating for a multiplier. In 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 (pp. 7-10). [5166253] https://doi.org/10.1109/ICICDT.2009.5166253

Implementation and evaluation of fine-grain run-time power gating for a multiplier. / Usami, Kimiyoshi; Nakata, Mitsutaka; Shirai, Toshiaki; Takeda, Seidai; Seki, Naomi; Amano, Hideharu; Nakamura, Hiroshi.

2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. 2009. p. 7-10 5166253.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Usami, K, Nakata, M, Shirai, T, Takeda, S, Seki, N, Amano, H & Nakamura, H 2009, Implementation and evaluation of fine-grain run-time power gating for a multiplier. in 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009., 5166253, pp. 7-10, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, Austin, TX, 09/5/18. https://doi.org/10.1109/ICICDT.2009.5166253
Usami K, Nakata M, Shirai T, Takeda S, Seki N, Amano H et al. Implementation and evaluation of fine-grain run-time power gating for a multiplier. In 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. 2009. p. 7-10. 5166253 https://doi.org/10.1109/ICICDT.2009.5166253
Usami, Kimiyoshi ; Nakata, Mitsutaka ; Shirai, Toshiaki ; Takeda, Seidai ; Seki, Naomi ; Amano, Hideharu ; Nakamura, Hiroshi. / Implementation and evaluation of fine-grain run-time power gating for a multiplier. 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. 2009. pp. 7-10
@inproceedings{9b211a3dfa494754a4c3f3dbaacd9146,
title = "Implementation and evaluation of fine-grain run-time power gating for a multiplier",
abstract = "In a 32bx32b multiplier, when the bit width of both operands is less than 16-bit, the upper array of the multiplier computing the upper bits of the product does not need to operate and hence consumes wasteful leakage energy. We propose a technique to control run-time power gating (RTPG) for the upper array by dynamically detecting the operand width. Since RTPG suffers from energy overhead due to turning on/off power switches, the sleep time at each sleep event should be longer than the break-even time (BET) to gain in energy savings. Using an analytical model we built, we show that BET reduces exponentially with higher temperature. Since the chip temperature goes up during the operation, the sleep time becomes more likely to exceed the shortened BET, leading to the increase of energy savings. We evaluated our technique through designing a 32bx32b multiplier and implementing in a commercial 90nm CMOS technology. Post-layout simulation results showed that BET reduces from 32 cycles at 25°C to 10 cycles at 65°C and to 3 cycles at 100°C at 100MHz. We also simulated energy dissipation by incorporating our multiplier into a MIPS R3000 based CPU and running a JPEG encoding program. Results showed that our technique reduces energy by 5{\%} at 65°C and by 39{\%} at 100°C over the PG-disabled case even counting the overhead. In contrast, energy was increased by 36{\%} at 25°C. The ground bounce at the wakeup was effectively suppressed to 91mV by using delay-skewed buffering for power switches, while achieving the wakeup time of 1.44ns.",
author = "Kimiyoshi Usami and Mitsutaka Nakata and Toshiaki Shirai and Seidai Takeda and Naomi Seki and Hideharu Amano and Hiroshi Nakamura",
year = "2009",
doi = "10.1109/ICICDT.2009.5166253",
language = "English",
isbn = "9781424429332",
pages = "7--10",
booktitle = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009",

}

TY - GEN

T1 - Implementation and evaluation of fine-grain run-time power gating for a multiplier

AU - Usami, Kimiyoshi

AU - Nakata, Mitsutaka

AU - Shirai, Toshiaki

AU - Takeda, Seidai

AU - Seki, Naomi

AU - Amano, Hideharu

AU - Nakamura, Hiroshi

PY - 2009

Y1 - 2009

N2 - In a 32bx32b multiplier, when the bit width of both operands is less than 16-bit, the upper array of the multiplier computing the upper bits of the product does not need to operate and hence consumes wasteful leakage energy. We propose a technique to control run-time power gating (RTPG) for the upper array by dynamically detecting the operand width. Since RTPG suffers from energy overhead due to turning on/off power switches, the sleep time at each sleep event should be longer than the break-even time (BET) to gain in energy savings. Using an analytical model we built, we show that BET reduces exponentially with higher temperature. Since the chip temperature goes up during the operation, the sleep time becomes more likely to exceed the shortened BET, leading to the increase of energy savings. We evaluated our technique through designing a 32bx32b multiplier and implementing in a commercial 90nm CMOS technology. Post-layout simulation results showed that BET reduces from 32 cycles at 25°C to 10 cycles at 65°C and to 3 cycles at 100°C at 100MHz. We also simulated energy dissipation by incorporating our multiplier into a MIPS R3000 based CPU and running a JPEG encoding program. Results showed that our technique reduces energy by 5% at 65°C and by 39% at 100°C over the PG-disabled case even counting the overhead. In contrast, energy was increased by 36% at 25°C. The ground bounce at the wakeup was effectively suppressed to 91mV by using delay-skewed buffering for power switches, while achieving the wakeup time of 1.44ns.

AB - In a 32bx32b multiplier, when the bit width of both operands is less than 16-bit, the upper array of the multiplier computing the upper bits of the product does not need to operate and hence consumes wasteful leakage energy. We propose a technique to control run-time power gating (RTPG) for the upper array by dynamically detecting the operand width. Since RTPG suffers from energy overhead due to turning on/off power switches, the sleep time at each sleep event should be longer than the break-even time (BET) to gain in energy savings. Using an analytical model we built, we show that BET reduces exponentially with higher temperature. Since the chip temperature goes up during the operation, the sleep time becomes more likely to exceed the shortened BET, leading to the increase of energy savings. We evaluated our technique through designing a 32bx32b multiplier and implementing in a commercial 90nm CMOS technology. Post-layout simulation results showed that BET reduces from 32 cycles at 25°C to 10 cycles at 65°C and to 3 cycles at 100°C at 100MHz. We also simulated energy dissipation by incorporating our multiplier into a MIPS R3000 based CPU and running a JPEG encoding program. Results showed that our technique reduces energy by 5% at 65°C and by 39% at 100°C over the PG-disabled case even counting the overhead. In contrast, energy was increased by 36% at 25°C. The ground bounce at the wakeup was effectively suppressed to 91mV by using delay-skewed buffering for power switches, while achieving the wakeup time of 1.44ns.

UR - http://www.scopus.com/inward/record.url?scp=77950330455&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77950330455&partnerID=8YFLogxK

U2 - 10.1109/ICICDT.2009.5166253

DO - 10.1109/ICICDT.2009.5166253

M3 - Conference contribution

AN - SCOPUS:77950330455

SN - 9781424429332

SP - 7

EP - 10

BT - 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

ER -