Improvement of simultaneous switching noise simulation considering on-chip capacitance

Kunio Ota, Kazuhisa Matsuge, Yo Takahashi, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Simultaneous switching noise (SSN) causes signal degradation to the high-speed interfaces among CMOS VLSIs. To achieve SSN simulation with a high accuracy, accurate models for chips, packages and printed circuit boards (PCBs) are required. However, such accurate simulation models are not currently available, since chip vendors do not release the value of on-chip capacitance and the detailed package model with mutual inductances. This paper presents our approach for establishing an accurate model without detailed information on the chip and package. The three key points of our approach are the measurement of on-chip capacitance using a vector network analyzer (VNA), the measurement of quad flat package (QFP) dimensions using X-ray photographs, and the application of 3-D electromagnetic field solver to extract a detailed equivalent circuit model for the package from a geometrical structure. The simulated SSN time-domain waveforms showed an extremely good agreement with the measured results.

Original languageEnglish
Title of host publicationIEEE International Symposium on Electromagnetic Compatibility
Pages284-288
Number of pages5
DOIs
Publication statusPublished - 2010
Event2010 IEEE International Symposium on Electromagnetic Compatibility, EMC 2010 - Fort Lauderdale, FL
Duration: 2010 Jul 252010 Jul 30

Other

Other2010 IEEE International Symposium on Electromagnetic Compatibility, EMC 2010
CityFort Lauderdale, FL
Period10/7/2510/7/30

Fingerprint

Capacitance
capacitance
chips
simulation
Electric network analyzers
printed circuits
circuit boards
very large scale integration
photographs
equivalent circuits
inductance
Equivalent circuits
Printed circuit boards
Inductance
Electromagnetic fields
analyzers
CMOS
waveforms
electromagnetic fields
high speed

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics

Cite this

Ota, K., Matsuge, K., Takahashi, Y., & Sudo, T. (2010). Improvement of simultaneous switching noise simulation considering on-chip capacitance. In IEEE International Symposium on Electromagnetic Compatibility (pp. 284-288). [5711286] https://doi.org/10.1109/ISEMC.2010.5711286

Improvement of simultaneous switching noise simulation considering on-chip capacitance. / Ota, Kunio; Matsuge, Kazuhisa; Takahashi, Yo; Sudo, Toshio.

IEEE International Symposium on Electromagnetic Compatibility. 2010. p. 284-288 5711286.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ota, K, Matsuge, K, Takahashi, Y & Sudo, T 2010, Improvement of simultaneous switching noise simulation considering on-chip capacitance. in IEEE International Symposium on Electromagnetic Compatibility., 5711286, pp. 284-288, 2010 IEEE International Symposium on Electromagnetic Compatibility, EMC 2010, Fort Lauderdale, FL, 10/7/25. https://doi.org/10.1109/ISEMC.2010.5711286
Ota K, Matsuge K, Takahashi Y, Sudo T. Improvement of simultaneous switching noise simulation considering on-chip capacitance. In IEEE International Symposium on Electromagnetic Compatibility. 2010. p. 284-288. 5711286 https://doi.org/10.1109/ISEMC.2010.5711286
Ota, Kunio ; Matsuge, Kazuhisa ; Takahashi, Yo ; Sudo, Toshio. / Improvement of simultaneous switching noise simulation considering on-chip capacitance. IEEE International Symposium on Electromagnetic Compatibility. 2010. pp. 284-288
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