Reduction of PDN impedance is necessary to prevent false logic operation of the CMOS LSIs. Constant target impedance with frequency is used as a simple method to define PDN impedance of the system. However, this conventional target impedance did not change with frequency, and was not applied to the high frequency range where PDN impedance exceeds the constant value of target impedance. Therefore, newly frequency dependent target impedance has been derived and applied to the DDR3 memory system. Co-simulation model has been established to estimate power Integrity (PI) and signal Integrity (SI) at the same time. The switching current flowing from the chip was connected to the whole PDN model, and power supply noise and eyes diagram were simulated. The new target impedance has been proved to be reasonable for maintaining the power supply noise and the eye diagrams.