Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

One of the benefits of coarse grained dynamically re-configurable processor array(DRPA) is its low dynamic power consumption by operating a number of processing elements(PE) in parallel with low clock frequency. However, in the future advanced processes, leakage power will occupy a considerable part of the total power consumption, and it may degrade the advantage of DRPAs. In order to reduce the leakage power, a fine grained Power Gating(PG) is applied to a DRPA, MuCCRA-2.32b, and leakage power and area overhead are measured. We evaluated the effect of two control modes; Pair and Unit Individual based on layout design and real applications. It appears that by applying PG for ALUs and SMUs in PEs individually, 48% of leakage power can be reduced with 9.0% of area overhead.

Original languageEnglish
Title of host publicationProceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008
Pages329-332
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 International Conference on Field-Programmable Technology, ICFPT 2008 - Taipei, Taiwan, Province of China
Duration: 2008 Dec 72008 Dec 10

Publication series

NameProceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008

Conference

Conference2008 International Conference on Field-Programmable Technology, ICFPT 2008
CountryTaiwan, Province of China
CityTaipei
Period08/12/708/12/10

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture

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    Saito, Y., Shirai, T., Nakamura, T., Nishimura, T., Hasegawa, Y., Tsutsumi, S., Kashima, T., Nakata, M., Takeda, S., Usami, K., & Amano, H. (2008). Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique. In Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008 (pp. 329-332). [4762410] (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008). https://doi.org/10.1109/FPT.2008.4762410