Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI

Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Level shifters to convert signal swings from low-voltage (VDDL) to high-voltage (VDDH) are required at the boundary of voltage domains in SoC employing multiple supply voltages. However, they cost delay, power and area in addition to increasing the complexity of physical design. This paper proposes a level-shifter-less (LSL) approach to use a reverse body bias (RBB) in the VDDH domain and superior threshold-voltage modulation capability of FD-SOI devices. Simulation results and measurements of a fabricated chip demonstrated that the chip applying the LSL approach correctly operates at VDDL=0.6V and VDDH=1.2V under RBB of 2V for pMOS transistors while suppressing the static dc current in the VDDH domain.

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Usami, K., Kogure, S., Yoshida, Y., Magasaki, R., & Amano, H. (2017). Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI. In 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings [8203473] IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2017.8203473