Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI

Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Level shifters to convert signal swings from low-voltage (VDDL) to high-voltage (VDDH) are required at the boundary of voltage domains in SoC employing multiple supply voltages. However, they cost delay, power and area in addition to increasing the complexity of physical design. This paper proposes a level-shifter-less (LSL) approach to use a reverse body bias (RBB) at pMOS transistors in the VDDH domain and superior threshold-voltage modulation capability of FD-SOI devices. Simulation results and measurements of a fabricated chip showed that the chip applying the LSL approach correctly operates at VDDL = 0.6 V and VDDH = 1.2 V under 2 V pMOS RBB while suppressing the static dc current in the VDDH domain. We also demonstrate that adaptive RBB control for pMOS can maintain effectiveness of this approach under process and temperature variations.

Original languageEnglish
Title of host publicationVLSI-SoC
Subtitle of host publicationOpportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Revised and Extended Selected Papers
EditorsJosé Monteiro, Ibrahim Abe M. Elfadel, Matteo Sonza Reorda, H. Fatih Ugurdag, Michail Maniatakos, Ricardo Reis
PublisherSpringer New York LLC
Pages1-21
Number of pages21
ISBN (Print)9783030156626
DOIs
Publication statusPublished - 2019 Jan 1
Event25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Abu Dhabi, United Arab Emirates
Duration: 2017 Oct 232017 Oct 25

Publication series

NameIFIP Advances in Information and Communication Technology
Volume500
ISSN (Print)1868-4238

Other

Other25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017
CountryUnited Arab Emirates
CityAbu Dhabi
Period17/10/2317/10/25

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Keywords

  • Body bias control
  • FD-SOI
  • Level shifter
  • Low power
  • Multi-VDD design
  • Variations

ASJC Scopus subject areas

  • Information Systems and Management

Cite this

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R., & Amano, H. (2019). Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI. In J. Monteiro, I. A. M. Elfadel, M. Sonza Reorda, H. F. Ugurdag, M. Maniatakos, & R. Reis (Eds.), VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Revised and Extended Selected Papers (pp. 1-21). (IFIP Advances in Information and Communication Technology; Vol. 500). Springer New York LLC. https://doi.org/10.1007/978-3-030-15663-3_1