Abstract
We evaluated low-impedance power distribution network (PDN) of decoupling capacitor embedded interposers for 3-D integrated LSI system. Measurements are carried out using the developed impedance analyzer system of a wide frequency range for evaluating ultralow impedance, and calculations are carried out using 2.5-D finite element method (FEM) electromagnetic field simulator. We fabricated various types of capacitor mounted or capacitor embedded interposers test element group (TEG), such as surfacemounted and embedded chip capacitors, and thin film capacitors on silicon interposers using the same simple design to compare measurement results with calculation ones. As a result, the chip capacitor embedded organic interposer TEG and thin film capacitor embedded silicon interposer TEG could provide low PDN impedance at a wide frequency range of up to 40 GHz. In particular, the interposer TEGs of the thin film capacitor embedded interposer that shows a low impedance of 0.1Ωcould be evaluated and calculated accurately. By using chip capacitor embedded or thin film capacitor embedded interposers for 3-D integrated LSI system, it is expected that the PDN of the system can be achieved ultralow PDN impedance.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - Electronic Components and Technology Conference |
| Pages | 1455-1460 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2010 |
| Event | 60th Electronic Components and Technology Conference, ECTC 2010 - Las Vegas, NV Duration: 2010 Jun 1 → 2010 Jun 4 |
Other
| Other | 60th Electronic Components and Technology Conference, ECTC 2010 |
|---|---|
| City | Las Vegas, NV |
| Period | 10/6/1 → 10/6/4 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
Low-impedance evaluation of power distribution network for decoupling capacitor embedded interposers of 3-D integrated LSI system. / Kikuchi, Katsuya; Ueda, Chihiro; Takemura, Koichi; Shimada, Osamu; Gomyo, Toshio; Takeuchi, Yukiharu; Ookubo, Toshikazu; Baba, Kazuhiro; Aoyagi, Masahiro; Sudo, Toshio; Otsuka, Kanji.
Proceedings - Electronic Components and Technology Conference. 2010. p. 1455-1460 5490807.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Low-impedance evaluation of power distribution network for decoupling capacitor embedded interposers of 3-D integrated LSI system
AU - Kikuchi, Katsuya
AU - Ueda, Chihiro
AU - Takemura, Koichi
AU - Shimada, Osamu
AU - Gomyo, Toshio
AU - Takeuchi, Yukiharu
AU - Ookubo, Toshikazu
AU - Baba, Kazuhiro
AU - Aoyagi, Masahiro
AU - Sudo, Toshio
AU - Otsuka, Kanji
PY - 2010
Y1 - 2010
N2 - We evaluated low-impedance power distribution network (PDN) of decoupling capacitor embedded interposers for 3-D integrated LSI system. Measurements are carried out using the developed impedance analyzer system of a wide frequency range for evaluating ultralow impedance, and calculations are carried out using 2.5-D finite element method (FEM) electromagnetic field simulator. We fabricated various types of capacitor mounted or capacitor embedded interposers test element group (TEG), such as surfacemounted and embedded chip capacitors, and thin film capacitors on silicon interposers using the same simple design to compare measurement results with calculation ones. As a result, the chip capacitor embedded organic interposer TEG and thin film capacitor embedded silicon interposer TEG could provide low PDN impedance at a wide frequency range of up to 40 GHz. In particular, the interposer TEGs of the thin film capacitor embedded interposer that shows a low impedance of 0.1Ωcould be evaluated and calculated accurately. By using chip capacitor embedded or thin film capacitor embedded interposers for 3-D integrated LSI system, it is expected that the PDN of the system can be achieved ultralow PDN impedance.
AB - We evaluated low-impedance power distribution network (PDN) of decoupling capacitor embedded interposers for 3-D integrated LSI system. Measurements are carried out using the developed impedance analyzer system of a wide frequency range for evaluating ultralow impedance, and calculations are carried out using 2.5-D finite element method (FEM) electromagnetic field simulator. We fabricated various types of capacitor mounted or capacitor embedded interposers test element group (TEG), such as surfacemounted and embedded chip capacitors, and thin film capacitors on silicon interposers using the same simple design to compare measurement results with calculation ones. As a result, the chip capacitor embedded organic interposer TEG and thin film capacitor embedded silicon interposer TEG could provide low PDN impedance at a wide frequency range of up to 40 GHz. In particular, the interposer TEGs of the thin film capacitor embedded interposer that shows a low impedance of 0.1Ωcould be evaluated and calculated accurately. By using chip capacitor embedded or thin film capacitor embedded interposers for 3-D integrated LSI system, it is expected that the PDN of the system can be achieved ultralow PDN impedance.
UR - http://www.scopus.com/inward/record.url?scp=77955225775&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77955225775&partnerID=8YFLogxK
U2 - 10.1109/ECTC.2010.5490807
DO - 10.1109/ECTC.2010.5490807
M3 - Conference contribution
SN - 9781424464104
SP - 1455
EP - 1460
BT - Proceedings - Electronic Components and Technology Conference
ER -