Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system

Katsuya Kikuchi, Koichi Takemura, Chihiro Ueda, Osamu Shimada, Toshio Gomyo, Yukiharu Takeuchi, Toshikazu Okubo, Kazuhiro Baba, Masahiro Aoyagi, Toshio Sudo, Kanji Otsuka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

We evaluated low-impedance power distribution network (PDN) of decoupling capacitor embedded interposers for 3-D integrated LSI system. Measurements are carried out using the developed impedance analyzer system of a wide frequency range for evaluating ultralow impedance, and calculations are carried out using 2.5-D finite element method (FEM) electromagnetic field simulator. We fabricated various types of capacitor mounted or capacitor embedded interposers test element group (TEG), such as surface-mounted and embedded chip capacitors, and thin film capacitors on silicon interposers using the same simple design to compare measurement results with calculation ones. As a result, the chip capacitor embedded organic interposer TEG and thin film capacitor embedded silicon interposer TEG could provide low PDN impedance at a wide frequency range of up to 10 GHz. In particular, the interposer TEGs of the thin film capacitor embedded interposer that shows a low impedance of approximately 0.001 ? could be evaluated and calculated accurately. By using chip capacitor embedded or thin film capacitor embedded interposers for 3-D integrated LSI system, it is expected that the PDN of the system can be achieved ultralow PDN impedance.

Original languageEnglish
Title of host publication2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09
Pages25-28
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09 - Portland, OR
Duration: 2009 Oct 192009 Oct 21

Other

Other2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09
CityPortland, OR
Period09/10/1909/10/21

Fingerprint

Electric power distribution
Capacitors
Silicon
Electromagnetic fields
Simulators
Finite element method
Film capacitor

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kikuchi, K., Takemura, K., Ueda, C., Shimada, O., Gomyo, T., Takeuchi, Y., ... Otsuka, K. (2009). Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system. In 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09 (pp. 25-28). [5338487] https://doi.org/10.1109/EPEPS.2009.5338487

Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system. / Kikuchi, Katsuya; Takemura, Koichi; Ueda, Chihiro; Shimada, Osamu; Gomyo, Toshio; Takeuchi, Yukiharu; Okubo, Toshikazu; Baba, Kazuhiro; Aoyagi, Masahiro; Sudo, Toshio; Otsuka, Kanji.

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09. 2009. p. 25-28 5338487.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kikuchi, K, Takemura, K, Ueda, C, Shimada, O, Gomyo, T, Takeuchi, Y, Okubo, T, Baba, K, Aoyagi, M, Sudo, T & Otsuka, K 2009, Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system. in 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09., 5338487, pp. 25-28, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09, Portland, OR, 09/10/19. https://doi.org/10.1109/EPEPS.2009.5338487
Kikuchi K, Takemura K, Ueda C, Shimada O, Gomyo T, Takeuchi Y et al. Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system. In 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09. 2009. p. 25-28. 5338487 https://doi.org/10.1109/EPEPS.2009.5338487
Kikuchi, Katsuya ; Takemura, Koichi ; Ueda, Chihiro ; Shimada, Osamu ; Gomyo, Toshio ; Takeuchi, Yukiharu ; Okubo, Toshikazu ; Baba, Kazuhiro ; Aoyagi, Masahiro ; Sudo, Toshio ; Otsuka, Kanji. / Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system. 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09. 2009. pp. 25-28
@inproceedings{c5cf4240bad5474caefd55afdb2bf5df,
title = "Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system",
abstract = "We evaluated low-impedance power distribution network (PDN) of decoupling capacitor embedded interposers for 3-D integrated LSI system. Measurements are carried out using the developed impedance analyzer system of a wide frequency range for evaluating ultralow impedance, and calculations are carried out using 2.5-D finite element method (FEM) electromagnetic field simulator. We fabricated various types of capacitor mounted or capacitor embedded interposers test element group (TEG), such as surface-mounted and embedded chip capacitors, and thin film capacitors on silicon interposers using the same simple design to compare measurement results with calculation ones. As a result, the chip capacitor embedded organic interposer TEG and thin film capacitor embedded silicon interposer TEG could provide low PDN impedance at a wide frequency range of up to 10 GHz. In particular, the interposer TEGs of the thin film capacitor embedded interposer that shows a low impedance of approximately 0.001 ? could be evaluated and calculated accurately. By using chip capacitor embedded or thin film capacitor embedded interposers for 3-D integrated LSI system, it is expected that the PDN of the system can be achieved ultralow PDN impedance.",
author = "Katsuya Kikuchi and Koichi Takemura and Chihiro Ueda and Osamu Shimada and Toshio Gomyo and Yukiharu Takeuchi and Toshikazu Okubo and Kazuhiro Baba and Masahiro Aoyagi and Toshio Sudo and Kanji Otsuka",
year = "2009",
doi = "10.1109/EPEPS.2009.5338487",
language = "English",
isbn = "9781424444472",
pages = "25--28",
booktitle = "2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09",

}

TY - GEN

T1 - Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system

AU - Kikuchi, Katsuya

AU - Takemura, Koichi

AU - Ueda, Chihiro

AU - Shimada, Osamu

AU - Gomyo, Toshio

AU - Takeuchi, Yukiharu

AU - Okubo, Toshikazu

AU - Baba, Kazuhiro

AU - Aoyagi, Masahiro

AU - Sudo, Toshio

AU - Otsuka, Kanji

PY - 2009

Y1 - 2009

N2 - We evaluated low-impedance power distribution network (PDN) of decoupling capacitor embedded interposers for 3-D integrated LSI system. Measurements are carried out using the developed impedance analyzer system of a wide frequency range for evaluating ultralow impedance, and calculations are carried out using 2.5-D finite element method (FEM) electromagnetic field simulator. We fabricated various types of capacitor mounted or capacitor embedded interposers test element group (TEG), such as surface-mounted and embedded chip capacitors, and thin film capacitors on silicon interposers using the same simple design to compare measurement results with calculation ones. As a result, the chip capacitor embedded organic interposer TEG and thin film capacitor embedded silicon interposer TEG could provide low PDN impedance at a wide frequency range of up to 10 GHz. In particular, the interposer TEGs of the thin film capacitor embedded interposer that shows a low impedance of approximately 0.001 ? could be evaluated and calculated accurately. By using chip capacitor embedded or thin film capacitor embedded interposers for 3-D integrated LSI system, it is expected that the PDN of the system can be achieved ultralow PDN impedance.

AB - We evaluated low-impedance power distribution network (PDN) of decoupling capacitor embedded interposers for 3-D integrated LSI system. Measurements are carried out using the developed impedance analyzer system of a wide frequency range for evaluating ultralow impedance, and calculations are carried out using 2.5-D finite element method (FEM) electromagnetic field simulator. We fabricated various types of capacitor mounted or capacitor embedded interposers test element group (TEG), such as surface-mounted and embedded chip capacitors, and thin film capacitors on silicon interposers using the same simple design to compare measurement results with calculation ones. As a result, the chip capacitor embedded organic interposer TEG and thin film capacitor embedded silicon interposer TEG could provide low PDN impedance at a wide frequency range of up to 10 GHz. In particular, the interposer TEGs of the thin film capacitor embedded interposer that shows a low impedance of approximately 0.001 ? could be evaluated and calculated accurately. By using chip capacitor embedded or thin film capacitor embedded interposers for 3-D integrated LSI system, it is expected that the PDN of the system can be achieved ultralow PDN impedance.

UR - http://www.scopus.com/inward/record.url?scp=74549125795&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=74549125795&partnerID=8YFLogxK

U2 - 10.1109/EPEPS.2009.5338487

DO - 10.1109/EPEPS.2009.5338487

M3 - Conference contribution

SN - 9781424444472

SP - 25

EP - 28

BT - 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09

ER -