Abstract
An ECL-compatible 10-Gbps GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) has been developed. To decrease power consumption and to maximize phase margin, the clock-generating circuit employs source-coupled FET logic (SCFL) circuits. Also, cascade-connected source-follower circuits are used in the clock buffer. These circuits can reduce the power consumption when the fan-out number is large. Direct coupled FET logic (DCFL) circuits are employed for the 2:1 MUX/1:2 DEMUX circuits operating below 5 Gbps. The ICs, which are mounted on ceramic packages, operate at up to 10 Gbps with a power consumption of 1.2 W for the MUX and 1.0 W for the DEMUX at ECL-compatible supply voltages. These power-consumption values are one-third of the previously reported values.
Original language | English |
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Pages | 113-116 |
Number of pages | 4 |
Publication status | Published - 1997 Dec 1 |
Externally published | Yes |
Event | Proceedings of the 1997 19th Annual GaAs IC Symposium - Anaheim, CA, USA Duration: 1997 Oct 12 → 1997 Oct 15 |
Other
Other | Proceedings of the 1997 19th Annual GaAs IC Symposium |
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City | Anaheim, CA, USA |
Period | 97/10/12 → 97/10/15 |
ASJC Scopus subject areas
- Engineering(all)