16:1 Multiplexer (MUX) and Demultiplexer (DMUX) for the STM-16 transmission system are designed by standard cell method using automatic layout CAD system, and fabricated using the developed 0.5 μm gate self-aligned process technology. The total numbers of the logic gates for MUX and DMUX are about 700 and 800, respectively. To realize high-speed operation with low power consumption and large noise margin tolerance, direct-coupled FET logic circuits are employed, which are based on author's proposed i-AlGaAs/n-GaAs Doped-channel hereto-MISFETs (DMTs). Fully functional operations are confirmed in a temperature range from 20 °C up to 75 °C with ±10% margin of supply voltage at -2 V and the ECL output levels. Obtained maximum speed is 1.4 Gbps for MUX and 1.1 Gbps for DMUX. Power consumption is 0.6 W and 0.9 W, respectively, which are about one third of those for LSIs reported so far. In addition, authors probe into the main causes of lower operation speed through high-speed direct probing measurements and simulations, and it is concluded that the expected operation speed of more than 2.5 Gbps can be achieved by minor changes in mask layout design.
|Title of host publication||NEC Research and Development|
|Number of pages||11|
|Publication status||Published - 1992 Jul 1|
ASJC Scopus subject areas
- Electrical and Electronic Engineering