Low-power design method using multiple supply voltages

Mutsunori Igarashi, Kimiyoshi Usami, Kazutaka Nogami, Fumihiro Minami, Yukio Kawasaki, Takahiro Aoki, Midori Takano, Chiharu Mizuno, Takashi Lshikawa, Masahiro Kanazawa, Shinji Sonoda, Makoto Ichida, Naoyuki Hatanaka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

50 Citations (Scopus)

Abstract

We present a low-power design method that utilizes the multiple supply voltages. The proposed method reduces the power consumption of random logic circuits by 47% on the average, with up to 15% area overhead, by the combination of `Clustered Voltage Scaling (CVS) scheme' and `Row by Row optimized Power Supply (RRPS) scheme'. By the CVS scheme, the optimal netlist, that uses the minimized number of the level converters and the maximized number of the low Vdd gates under the timing constraints, is generated. To avoid the wiring resource consumption and the increase of the interconnect delay caused by the layout constraints of the multiple-supply-voltage design, a new power bus wiring scheme called `RRPS scheme' is proposed. The proposed method is applied to a media processor chip MpactTM and achieved the above mentioned results. In this paper, the emphasis is put on the interrelation between the generation of the two-supply-voltage netlist with the CVS scheme and the layout technology, such as the power supply scheme and the placement of the multiple-supply- voltage gates. The clocking scheme for the multiple supply voltages is also discussed.

Original languageEnglish
Title of host publicationInternational Symposium on Low Power Electronics and Design, Digest of Technical Papers
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages36-41
Number of pages6
Publication statusPublished - 1997
Externally publishedYes
EventProceedings of the 1997 International Symposium on Low Power Electronics and Design - Monterey, CA, USA
Duration: 1997 Aug 181997 Aug 20

Other

OtherProceedings of the 1997 International Symposium on Low Power Electronics and Design
CityMonterey, CA, USA
Period97/8/1897/8/20

Fingerprint

Electric potential
Electric wiring
Logic circuits
Electric power utilization
Voltage scaling

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Igarashi, M., Usami, K., Nogami, K., Minami, F., Kawasaki, Y., Aoki, T., ... Hatanaka, N. (1997). Low-power design method using multiple supply voltages. In International Symposium on Low Power Electronics and Design, Digest of Technical Papers (pp. 36-41). Piscataway, NJ, United States: IEEE.

Low-power design method using multiple supply voltages. / Igarashi, Mutsunori; Usami, Kimiyoshi; Nogami, Kazutaka; Minami, Fumihiro; Kawasaki, Yukio; Aoki, Takahiro; Takano, Midori; Mizuno, Chiharu; Lshikawa, Takashi; Kanazawa, Masahiro; Sonoda, Shinji; Ichida, Makoto; Hatanaka, Naoyuki.

International Symposium on Low Power Electronics and Design, Digest of Technical Papers. Piscataway, NJ, United States : IEEE, 1997. p. 36-41.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Igarashi, M, Usami, K, Nogami, K, Minami, F, Kawasaki, Y, Aoki, T, Takano, M, Mizuno, C, Lshikawa, T, Kanazawa, M, Sonoda, S, Ichida, M & Hatanaka, N 1997, Low-power design method using multiple supply voltages. in International Symposium on Low Power Electronics and Design, Digest of Technical Papers. IEEE, Piscataway, NJ, United States, pp. 36-41, Proceedings of the 1997 International Symposium on Low Power Electronics and Design, Monterey, CA, USA, 97/8/18.
Igarashi M, Usami K, Nogami K, Minami F, Kawasaki Y, Aoki T et al. Low-power design method using multiple supply voltages. In International Symposium on Low Power Electronics and Design, Digest of Technical Papers. Piscataway, NJ, United States: IEEE. 1997. p. 36-41
Igarashi, Mutsunori ; Usami, Kimiyoshi ; Nogami, Kazutaka ; Minami, Fumihiro ; Kawasaki, Yukio ; Aoki, Takahiro ; Takano, Midori ; Mizuno, Chiharu ; Lshikawa, Takashi ; Kanazawa, Masahiro ; Sonoda, Shinji ; Ichida, Makoto ; Hatanaka, Naoyuki. / Low-power design method using multiple supply voltages. International Symposium on Low Power Electronics and Design, Digest of Technical Papers. Piscataway, NJ, United States : IEEE, 1997. pp. 36-41
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AU - Aoki, Takahiro

AU - Takano, Midori

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N2 - We present a low-power design method that utilizes the multiple supply voltages. The proposed method reduces the power consumption of random logic circuits by 47% on the average, with up to 15% area overhead, by the combination of `Clustered Voltage Scaling (CVS) scheme' and `Row by Row optimized Power Supply (RRPS) scheme'. By the CVS scheme, the optimal netlist, that uses the minimized number of the level converters and the maximized number of the low Vdd gates under the timing constraints, is generated. To avoid the wiring resource consumption and the increase of the interconnect delay caused by the layout constraints of the multiple-supply-voltage design, a new power bus wiring scheme called `RRPS scheme' is proposed. The proposed method is applied to a media processor chip MpactTM and achieved the above mentioned results. In this paper, the emphasis is put on the interrelation between the generation of the two-supply-voltage netlist with the CVS scheme and the layout technology, such as the power supply scheme and the placement of the multiple-supply- voltage gates. The clocking scheme for the multiple supply voltages is also discussed.

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