Low-power design methodology and applications utilizing dual supply voltages

Kimiyoshi Usami, Mutsunori Igarashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Citations (Scopus)

Abstract

This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview on existing low-power EDA technologies as background and discuss advantages and challenges of the dual-VDD approach. Through real design examples, we will show that the approach reduces power effectively while keeping the performance at negligible area overhead.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages123-128
Number of pages6
DOIs
Publication statusPublished - 2000
Externally publishedYes
Event2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 - Yokohama
Duration: 2000 Jan 252000 Jan 28

Other

Other2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
CityYokohama
Period00/1/2500/1/28

Fingerprint

Flip flop circuits
Electric potential
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Usami, K., & Igarashi, M. (2000). Low-power design methodology and applications utilizing dual supply voltages. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 123-128) https://doi.org/10.1145/368434.368590

Low-power design methodology and applications utilizing dual supply voltages. / Usami, Kimiyoshi; Igarashi, Mutsunori.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2000. p. 123-128.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Usami, K & Igarashi, M 2000, Low-power design methodology and applications utilizing dual supply voltages. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. pp. 123-128, 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000, Yokohama, 00/1/25. https://doi.org/10.1145/368434.368590
Usami K, Igarashi M. Low-power design methodology and applications utilizing dual supply voltages. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2000. p. 123-128 https://doi.org/10.1145/368434.368590
Usami, Kimiyoshi ; Igarashi, Mutsunori. / Low-power design methodology and applications utilizing dual supply voltages. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2000. pp. 123-128
@inproceedings{427421f9f4264f3c951b5a6c8d675e81,
title = "Low-power design methodology and applications utilizing dual supply voltages",
abstract = "This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview on existing low-power EDA technologies as background and discuss advantages and challenges of the dual-VDD approach. Through real design examples, we will show that the approach reduces power effectively while keeping the performance at negligible area overhead.",
author = "Kimiyoshi Usami and Mutsunori Igarashi",
year = "2000",
doi = "10.1145/368434.368590",
language = "English",
isbn = "0780359747",
pages = "123--128",
booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

}

TY - GEN

T1 - Low-power design methodology and applications utilizing dual supply voltages

AU - Usami, Kimiyoshi

AU - Igarashi, Mutsunori

PY - 2000

Y1 - 2000

N2 - This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview on existing low-power EDA technologies as background and discuss advantages and challenges of the dual-VDD approach. Through real design examples, we will show that the approach reduces power effectively while keeping the performance at negligible area overhead.

AB - This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview on existing low-power EDA technologies as background and discuss advantages and challenges of the dual-VDD approach. Through real design examples, we will show that the approach reduces power effectively while keeping the performance at negligible area overhead.

UR - http://www.scopus.com/inward/record.url?scp=0010893420&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0010893420&partnerID=8YFLogxK

U2 - 10.1145/368434.368590

DO - 10.1145/368434.368590

M3 - Conference contribution

AN - SCOPUS:0010893420

SN - 0780359747

SN - 9780780359741

SP - 123

EP - 128

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

ER -