Low-power design methodology and applications utilizing dual supply voltages

Kimiyoshi Usami, Mutsunori Igarashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Citations (Scopus)

Abstract

This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview on existing low-power EDA technologies as background and discuss advantages and challenges of the dual-VDD approach. Through real design examples, we will show that the approach reduces power effectively while keeping the performance at negligible area overhead.

Original languageEnglish
Title of host publicationProceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
Pages123-128
Number of pages6
DOIs
Publication statusPublished - 2000 Dec 1
Event2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 - Yokohama, Japan
Duration: 2000 Jan 252000 Jan 28

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
CountryJapan
CityYokohama
Period00/1/2500/1/28

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • Cite this

    Usami, K., & Igarashi, M. (2000). Low-power design methodology and applications utilizing dual supply voltages. In Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 (pp. 123-128). (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1145/368434.368590