Low-power design technique for ASICs by partially reducing supply voltage

Kimiyoshi Usami, Takashi Ishikawa, Masahiro Kanazawa, Hiroko Kotani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)

Abstract

In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.

Original languageEnglish
Title of host publicationProceedings of the Annual IEEE International ASIC Conference and Exhibit
EditorsJ.D. Meindl, P.R. Mukund, T. Gabara, R. Sridhar
Pages301-304
Number of pages4
Publication statusPublished - 1996
Externally publishedYes
EventProceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA
Duration: 1996 Sep 231996 Sep 27

Other

OtherProceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit
CityRochester, NY, USA
Period96/9/2396/9/27

Fingerprint

Application specific integrated circuits
Electric potential
Capacitance
Wire
Degradation
Voltage scaling
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Usami, K., Ishikawa, T., Kanazawa, M., & Kotani, H. (1996). Low-power design technique for ASICs by partially reducing supply voltage. In J. D. Meindl, P. R. Mukund, T. Gabara, & R. Sridhar (Eds.), Proceedings of the Annual IEEE International ASIC Conference and Exhibit (pp. 301-304)

Low-power design technique for ASICs by partially reducing supply voltage. / Usami, Kimiyoshi; Ishikawa, Takashi; Kanazawa, Masahiro; Kotani, Hiroko.

Proceedings of the Annual IEEE International ASIC Conference and Exhibit. ed. / J.D. Meindl; P.R. Mukund; T. Gabara; R. Sridhar. 1996. p. 301-304.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Usami, K, Ishikawa, T, Kanazawa, M & Kotani, H 1996, Low-power design technique for ASICs by partially reducing supply voltage. in JD Meindl, PR Mukund, T Gabara & R Sridhar (eds), Proceedings of the Annual IEEE International ASIC Conference and Exhibit. pp. 301-304, Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit, Rochester, NY, USA, 96/9/23.
Usami K, Ishikawa T, Kanazawa M, Kotani H. Low-power design technique for ASICs by partially reducing supply voltage. In Meindl JD, Mukund PR, Gabara T, Sridhar R, editors, Proceedings of the Annual IEEE International ASIC Conference and Exhibit. 1996. p. 301-304
Usami, Kimiyoshi ; Ishikawa, Takashi ; Kanazawa, Masahiro ; Kotani, Hiroko. / Low-power design technique for ASICs by partially reducing supply voltage. Proceedings of the Annual IEEE International ASIC Conference and Exhibit. editor / J.D. Meindl ; P.R. Mukund ; T. Gabara ; R. Sridhar. 1996. pp. 301-304
@inproceedings{be8267a4f6574834910ca45d2249c760,
title = "Low-power design technique for ASICs by partially reducing supply voltage",
abstract = "In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60{\%} even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.",
author = "Kimiyoshi Usami and Takashi Ishikawa and Masahiro Kanazawa and Hiroko Kotani",
year = "1996",
language = "English",
pages = "301--304",
editor = "J.D. Meindl and P.R. Mukund and T. Gabara and R. Sridhar",
booktitle = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

}

TY - GEN

T1 - Low-power design technique for ASICs by partially reducing supply voltage

AU - Usami, Kimiyoshi

AU - Ishikawa, Takashi

AU - Kanazawa, Masahiro

AU - Kotani, Hiroko

PY - 1996

Y1 - 1996

N2 - In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.

AB - In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.

UR - http://www.scopus.com/inward/record.url?scp=0029726316&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029726316&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0029726316

SP - 301

EP - 304

BT - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

A2 - Meindl, J.D.

A2 - Mukund, P.R.

A2 - Gabara, T.

A2 - Sridhar, R.

ER -