Low-power design technique for ASICs by partially reducing supply voltage

Kimiyoshi Usami, Takashi Ishikawa, Masahiro Kanazawa, Hiroko Kotani

Research output: Contribution to journalConference article

24 Citations (Scopus)

Abstract

In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.

Original languageEnglish
Pages (from-to)301-304
Number of pages4
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
Publication statusPublished - 1996 Jan 1
Externally publishedYes
EventProceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA
Duration: 1996 Sep 231996 Sep 27

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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