Abstract
In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
| Editors | J.D. Meindl, P.R. Mukund, T. Gabara, R. Sridhar |
| Pages | 301-304 |
| Number of pages | 4 |
| Publication status | Published - 1996 |
| Externally published | Yes |
| Event | Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA Duration: 1996 Sep 23 → 1996 Sep 27 |
Other
| Other | Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit |
|---|---|
| City | Rochester, NY, USA |
| Period | 96/9/23 → 96/9/27 |
Fingerprint
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Low-power design technique for ASICs by partially reducing supply voltage. / Usami, Kimiyoshi; Ishikawa, Takashi; Kanazawa, Masahiro; Kotani, Hiroko.
Proceedings of the Annual IEEE International ASIC Conference and Exhibit. ed. / J.D. Meindl; P.R. Mukund; T. Gabara; R. Sridhar. 1996. p. 301-304.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Low-power design technique for ASICs by partially reducing supply voltage
AU - Usami, Kimiyoshi
AU - Ishikawa, Takashi
AU - Kanazawa, Masahiro
AU - Kotani, Hiroko
PY - 1996
Y1 - 1996
N2 - In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.
AB - In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.
UR - http://www.scopus.com/inward/record.url?scp=0029726316&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0029726316&partnerID=8YFLogxK
M3 - Conference contribution
SP - 301
EP - 304
BT - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
A2 - Meindl, J.D.
A2 - Mukund, P.R.
A2 - Gabara, T.
A2 - Sridhar, R.
ER -