Abstract
In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.
| Original language | English |
|---|---|
| Pages (from-to) | 301-304 |
| Number of pages | 4 |
| Journal | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
| Publication status | Published - 1996 Jan 1 |
| Externally published | Yes |
| Event | Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA Duration: 1996 Sep 23 → 1996 Sep 27 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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Cite this
Usami, K., Ishikawa, T., Kanazawa, M., & Kotani, H. (1996). Low-power design technique for ASICs by partially reducing supply voltage. Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 301-304.