Low-power technique for on-chip memory using biased partitioning and access concentration

Naoyuki Kawabe, Kimiyoshi Usami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different size of two sub-arrays by inserting transfer-gate into a bit-line. When smaller array is accessed, larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 Codec LSI. Power consumption was reduced by 40%.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherIEEE
Pages275-278
Number of pages4
Publication statusPublished - 2000
Externally publishedYes
EventCICC 2000: 22nd Annual Custom Integrated Circuits Conference - Orlando, FL, USA
Duration: 2000 May 212000 May 24

Other

OtherCICC 2000: 22nd Annual Custom Integrated Circuits Conference
CityOrlando, FL, USA
Period00/5/2100/5/24

Fingerprint

Data storage equipment
Electric power utilization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kawabe, N., & Usami, K. (2000). Low-power technique for on-chip memory using biased partitioning and access concentration. In Proceedings of the Custom Integrated Circuits Conference (pp. 275-278). IEEE.

Low-power technique for on-chip memory using biased partitioning and access concentration. / Kawabe, Naoyuki; Usami, Kimiyoshi.

Proceedings of the Custom Integrated Circuits Conference. IEEE, 2000. p. 275-278.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kawabe, N & Usami, K 2000, Low-power technique for on-chip memory using biased partitioning and access concentration. in Proceedings of the Custom Integrated Circuits Conference. IEEE, pp. 275-278, CICC 2000: 22nd Annual Custom Integrated Circuits Conference, Orlando, FL, USA, 00/5/21.
Kawabe N, Usami K. Low-power technique for on-chip memory using biased partitioning and access concentration. In Proceedings of the Custom Integrated Circuits Conference. IEEE. 2000. p. 275-278
Kawabe, Naoyuki ; Usami, Kimiyoshi. / Low-power technique for on-chip memory using biased partitioning and access concentration. Proceedings of the Custom Integrated Circuits Conference. IEEE, 2000. pp. 275-278
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