Low-power technique for on-chip memory using biased partitioning and access concentration

Naoyuki Kawabe, Kimiyoshi Usami

Research output: Contribution to journalConference article

6 Citations (Scopus)

Abstract

In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different size of two sub-arrays by inserting transfer-gate into a bit-line. When smaller array is accessed, larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 Codec LSI. Power consumption was reduced by 40%.

Original languageEnglish
Pages (from-to)275-278
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 2000 Jan 1
EventCICC 2000: 22nd Annual Custom Integrated Circuits Conference - Orlando, FL, USA
Duration: 2000 May 212000 May 24

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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