Low-power technique for on-chip memory using biased partitioning and access concentration

Naoyuki Kawabe; Kimiyoshi Usami

Low-power technique for on-chip memory using biased partitioning and access concentration

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different size of two sub-arrays by inserting transfer-gate into a bit-line. When smaller array is accessed, larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 Codec LSI. Power consumption was reduced by 40%.

Original language	English
Pages (from-to)	275-278
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 2000 Jan 1
Externally published	Yes
Event	CICC 2000: 22nd Annual Custom Integrated Circuits Conference - Orlando, FL, USA Duration: 2000 May 21 → 2000 May 24

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Low-power technique for on-chip memory using biased partitioning and access concentration",

abstract = "In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different size of two sub-arrays by inserting transfer-gate into a bit-line. When smaller array is accessed, larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 Codec LSI. Power consumption was reduced by 40%.",

author = "Naoyuki Kawabe and Kimiyoshi Usami",

year = "2000",

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language = "English",

pages = "275--278",

journal = "Proceedings of the Custom Integrated Circuits Conference",

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note = "CICC 2000: 22nd Annual Custom Integrated Circuits Conference ; Conference date: 21-05-2000 Through 24-05-2000",

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AU - Usami, Kimiyoshi

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N2 - In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different size of two sub-arrays by inserting transfer-gate into a bit-line. When smaller array is accessed, larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 Codec LSI. Power consumption was reduced by 40%.

AB - In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different size of two sub-arrays by inserting transfer-gate into a bit-line. When smaller array is accessed, larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 Codec LSI. Power consumption was reduced by 40%.

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AN - SCOPUS:0033711828

SN - 0886-5930

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EP - 278

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JF - Proceedings of the Custom Integrated Circuits Conference

T2 - CICC 2000: 22nd Annual Custom Integrated Circuits Conference

Y2 - 21 May 2000 through 24 May 2000

ER -

Low-power technique for on-chip memory using biased partitioning and access concentration

Abstract

ASJC Scopus subject areas

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