In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different size of two sub-arrays by inserting transfer-gate into a bit-line. When smaller array is accessed, larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 Codec LSI. Power consumption was reduced by 40%.
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|Publication status||Published - 2000 Jan 1|
|Event||CICC 2000: 22nd Annual Custom Integrated Circuits Conference - Orlando, FL, USA|
Duration: 2000 May 21 → 2000 May 24
ASJC Scopus subject areas
- Electrical and Electronic Engineering