This paper discusses the selection of the optimal device for LSI implementation of Viterbi decoder. The relation between the available number of gates and the performance of the decoder is described. A method of reducing the number of gates for low- and high-speed LSI decoders, as well as their major performance, is described. The developed LSI operates at the frequency of 25 MHz or higher. It is applicable generally to the error correction with (N - 1)/N coding rate. Compared with the Viterbi decoder using the same kind of LSI, the proposed LSI minimizes the number of chips and improves the speed by a factor of 1.5.
|Number of pages||11|
|Journal||Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)|
|Publication status||Published - 1990 Feb|
ASJC Scopus subject areas
- Electrical and Electronic Engineering