Material and process challenges for interconnects in nanoelectronics era

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Cu/low-k interconnects have been used in LSI fabrication. However, several difficult challenges need to be overcome for 22-nm node devices and beyond. These challenges include an increase in resistivity, degradation of the electromigration reliability, and the low mechanical strength of low-k dielectrics. To overcome these problems, it is essential to not only improve Cu/low-k fabrication processes but also to develop alternative approaches based on emerging technologies such as 3D interconnects, nanocarbon interconnects, and optical interconnects. This paper reviews the problems and potential solutions, and describes approaches such as supercritical (SC) annealing for grain growth enhancement, CoWP caps for electromigration (EM) reliability improvement, and electroless barrier deposition for ultrathin barrier layer.

Original languageEnglish
Title of host publicationProceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
Pages64-65
Number of pages2
DOIs
Publication statusPublished - 2010
Event2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 - Hsin Chu
Duration: 2010 Apr 262010 Apr 28

Other

Other2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
CityHsin Chu
Period10/4/2610/4/28

Fingerprint

Nanoelectronics
Electromigration
Fabrication
Optical interconnects
Grain growth
Strength of materials
Annealing
Degradation
Low-k dielectric

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Ueno, K. (2010). Material and process challenges for interconnects in nanoelectronics era. In Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 (pp. 64-65). [5488945] https://doi.org/10.1109/VTSA.2010.5488945

Material and process challenges for interconnects in nanoelectronics era. / Ueno, Kazuyoshi.

Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010. 2010. p. 64-65 5488945.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ueno, K 2010, Material and process challenges for interconnects in nanoelectronics era. in Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010., 5488945, pp. 64-65, 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010, Hsin Chu, 10/4/26. https://doi.org/10.1109/VTSA.2010.5488945
Ueno K. Material and process challenges for interconnects in nanoelectronics era. In Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010. 2010. p. 64-65. 5488945 https://doi.org/10.1109/VTSA.2010.5488945
Ueno, Kazuyoshi. / Material and process challenges for interconnects in nanoelectronics era. Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010. 2010. pp. 64-65
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