Material and Process Challenges for Interconnects in Nanoelectronics Era (Invited)

Research output: Contribution to journalArticle

Original languageEnglish
Pages (from-to)64-65
JournalProc. 2010 International Symposium on VLSI Technology, Systems and Applications
Publication statusPublished - 2010 Apr 26

Cite this

@article{4802f760cc7f497ab6c41f42dbab6d6c,
title = "Material and Process Challenges for Interconnects in Nanoelectronics Era (Invited)",
author = "Kazuyoshi Ueno",
year = "2010",
month = "4",
day = "26",
language = "English",
pages = "64--65",
journal = "Proc. 2010 International Symposium on VLSI Technology, Systems and Applications",

}

TY - JOUR

T1 - Material and Process Challenges for Interconnects in Nanoelectronics Era (Invited)

AU - Ueno, Kazuyoshi

PY - 2010/4/26

Y1 - 2010/4/26

M3 - Article

SP - 64

EP - 65

JO - Proc. 2010 International Symposium on VLSI Technology, Systems and Applications

JF - Proc. 2010 International Symposium on VLSI Technology, Systems and Applications

ER -