Measurement and modeling for MOS reverse current of switching DC/DC converter

Masahiro Terasaki, Yuta Oohashi, You Masuyama, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

DC/DC converters are widely used to produce various power supply voltages required for various electronic components on a board. Though DC/DC converter is more efficient than the linear regulator is, however, the switching noise becomes larger with the increase of the switching frequency. In particular, ringing noises at the sharp rising edge of the switching waveform generated by the effect of the parasitic inductance becomes a serious issue. This noise spreads out to the whole circuit board, and then generates electromagnetic interference (EMI), which often causes a malfunction of the electronic systems. In this paper, the methods to accurately reproduce the switching waveforms and to reduce ringing noises and resulting EMI from DC/DC converters were investigated. For this purpose, several evaluation boards were designed, and total electrical model was constructed by taking into account the parasitic inductances of traces on a board. First, frequency-domain analysis for the switching loop of the DC/DC converters was executed to find the optimum condition to suppress ringing noise effectively. Next, time-domain simulation was executed by considering the recovering time of MOS reverse current, which is not provided from device vendors. Finally, measured switching waveforms were well correlated with the simulated ones, and the optimal condition to suppress the ringing noise.

Original languageEnglish
Title of host publicationIEEE CPMT Symposium Japan 2014 - The Leading International Components, Packaging, and Manufacturing Technology Symposium: "Packaging for Future Optoelectronics, RF/High-Speed Electronics and Bioelectronics", ICSJ 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages87-90
Number of pages4
ISBN (Print)9781479961955
DOIs
Publication statusPublished - 2015 Jan 13
Event2014 4th IEEE CPMT Symposium Japan, ICSJ 2014 - Kyoto
Duration: 2014 Nov 42014 Nov 6

Other

Other2014 4th IEEE CPMT Symposium Japan, ICSJ 2014
CityKyoto
Period14/11/414/11/6

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Keywords

  • MOS Reverse Current
  • Noise Suppression
  • Parasitic Inductance
  • Ringing Noise
  • Switching Loop

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Terasaki, M., Oohashi, Y., Masuyama, Y., & Sudo, T. (2015). Measurement and modeling for MOS reverse current of switching DC/DC converter. In IEEE CPMT Symposium Japan 2014 - The Leading International Components, Packaging, and Manufacturing Technology Symposium: "Packaging for Future Optoelectronics, RF/High-Speed Electronics and Bioelectronics", ICSJ 2014 (pp. 87-90). [7009616] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSJ.2014.7009616