Measurement of SSO noise and PDN impedance of 3D SiP with 4k-IO widebus structure

Yosuke Tanaka, Hiroki Takatani, Haruya Fujita, Yoshiaki Oizono, Yoshitaka Nabeshima, Toshio Sudo, Atsushi Sakai, Shiro Uchiyama, Hiroaki Ikeda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Simultaneous switching output buffer (SSO) noise and impedance of power distribution network (PDN) for a 3D systemin package (SiP) with 4k-IO widebus structure has been investigated. The 3D SiP consisted of 3 stacked chips and an organic interposer. These three chips were a memory chip on the top, a silicon interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer. Next, these 3 stacked chips were assembled on the organic interposer, whose size was 26 mm by 26mm. SSO noise is one of critical issues for the 3D SiP with 4k-IO widebus structure. So, the SSO noise was measured in the miniIO power supply system in an evaluation board. Furthermore the PDN impedance for each chip was measured by direct contact method. Then, the total PDN impedance was synthesized to confirm the anti-resonance peak of it.

Original languageEnglish
Title of host publication2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
Pages91-94
Number of pages4
DOIs
Publication statusPublished - 2012
Event2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012 - Tempe, AZ
Duration: 2012 Oct 212012 Oct 24

Other

Other2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
CityTempe, AZ
Period12/10/2112/10/24

Fingerprint

Electric power distribution
Silicon
Electric power systems
Data storage equipment

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Tanaka, Y., Takatani, H., Fujita, H., Oizono, Y., Nabeshima, Y., Sudo, T., ... Ikeda, H. (2012). Measurement of SSO noise and PDN impedance of 3D SiP with 4k-IO widebus structure. In 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012 (pp. 91-94). [6457850] https://doi.org/10.1109/EPEPS.2012.6457850

Measurement of SSO noise and PDN impedance of 3D SiP with 4k-IO widebus structure. / Tanaka, Yosuke; Takatani, Hiroki; Fujita, Haruya; Oizono, Yoshiaki; Nabeshima, Yoshitaka; Sudo, Toshio; Sakai, Atsushi; Uchiyama, Shiro; Ikeda, Hiroaki.

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012. 2012. p. 91-94 6457850.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tanaka, Y, Takatani, H, Fujita, H, Oizono, Y, Nabeshima, Y, Sudo, T, Sakai, A, Uchiyama, S & Ikeda, H 2012, Measurement of SSO noise and PDN impedance of 3D SiP with 4k-IO widebus structure. in 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012., 6457850, pp. 91-94, 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012, Tempe, AZ, 12/10/21. https://doi.org/10.1109/EPEPS.2012.6457850
Tanaka Y, Takatani H, Fujita H, Oizono Y, Nabeshima Y, Sudo T et al. Measurement of SSO noise and PDN impedance of 3D SiP with 4k-IO widebus structure. In 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012. 2012. p. 91-94. 6457850 https://doi.org/10.1109/EPEPS.2012.6457850
Tanaka, Yosuke ; Takatani, Hiroki ; Fujita, Haruya ; Oizono, Yoshiaki ; Nabeshima, Yoshitaka ; Sudo, Toshio ; Sakai, Atsushi ; Uchiyama, Shiro ; Ikeda, Hiroaki. / Measurement of SSO noise and PDN impedance of 3D SiP with 4k-IO widebus structure. 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012. 2012. pp. 91-94
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AU - Nabeshima, Yoshitaka

AU - Sudo, Toshio

AU - Sakai, Atsushi

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