Minimization of Effective Inductance of Ground Plane and Experimental Simultaneous Switching Noise in a Multilayer VLSI Package,

Y.Hiruta Y.Hiruta, N.Hirano N.Hirano, T.Sudo T.Sudo, Toshio Sudo

Research output: Contribution to journalArticle

Original languageEnglish
JournalVLSI Packaging Workshop Japan
Publication statusPublished - 1992 Dec 1

Cite this

Minimization of Effective Inductance of Ground Plane and Experimental Simultaneous Switching Noise in a Multilayer VLSI Package, / Y.Hiruta, Y.Hiruta; N.Hirano, N.Hirano; T.Sudo, T.Sudo; Sudo, Toshio.

In: VLSI Packaging Workshop Japan, 01.12.1992.

Research output: Contribution to journalArticle

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