Multi bit PWMDAC with multi delay inverter

Daichi Kodama; Eri Ioka; Yasuyuki Matsuya

doi:10.1541/ieejeiss.133.239

Multi bit PWMDAC with multi delay inverter

Daichi Kodama, Eri Ioka, Yasuyuki Matsuya

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

The conventional local PWM-DAC for the ΔΣ D/A converter generates the PWM wave by dividing the clock signal. In this method, the sampling speed is decreased greatly by increasing the resolution. In this paper, we propose a new PWM-DAC with the Multi-Delay inverter. This DAC does not require the dividing clock as the conventional PWM-DAC. As simulation results, we show that the 5-th order ΔΣ D/A converter with the propose DAC achieves the S/N of 130 dB at the MOS transistor threshold voltage deviation of 100 mV.

Original language	English
Pages (from-to)	239-244
Number of pages	6
Journal	IEEJ Transactions on Electronics, Information and Systems
Volume	133
Issue number	2
DOIs	https://doi.org/10.1541/ieejeiss.133.239
Publication status	Published - 2013
Externally published	Yes

Keywords

Data weighted averaging
Digital-to-analog converter
Multi delay inverter
Pulse width modulation

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1541/ieejeiss.133.239

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title = "Multi bit PWMDAC with multi delay inverter",

abstract = "The conventional local PWM-DAC for the ΔΣ D/A converter generates the PWM wave by dividing the clock signal. In this method, the sampling speed is decreased greatly by increasing the resolution. In this paper, we propose a new PWM-DAC with the Multi-Delay inverter. This DAC does not require the dividing clock as the conventional PWM-DAC. As simulation results, we show that the 5-th order ΔΣ D/A converter with the propose DAC achieves the S/N of 130 dB at the MOS transistor threshold voltage deviation of 100 mV.",

keywords = "Data weighted averaging, Digital-to-analog converter, Multi delay inverter, Pulse width modulation",

author = "Daichi Kodama and Eri Ioka and Yasuyuki Matsuya",

year = "2013",

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language = "English",

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T1 - Multi bit PWMDAC with multi delay inverter

AU - Kodama, Daichi

AU - Ioka, Eri

AU - Matsuya, Yasuyuki

PY - 2013

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N2 - The conventional local PWM-DAC for the ΔΣ D/A converter generates the PWM wave by dividing the clock signal. In this method, the sampling speed is decreased greatly by increasing the resolution. In this paper, we propose a new PWM-DAC with the Multi-Delay inverter. This DAC does not require the dividing clock as the conventional PWM-DAC. As simulation results, we show that the 5-th order ΔΣ D/A converter with the propose DAC achieves the S/N of 130 dB at the MOS transistor threshold voltage deviation of 100 mV.

AB - The conventional local PWM-DAC for the ΔΣ D/A converter generates the PWM wave by dividing the clock signal. In this method, the sampling speed is decreased greatly by increasing the resolution. In this paper, we propose a new PWM-DAC with the Multi-Delay inverter. This DAC does not require the dividing clock as the conventional PWM-DAC. As simulation results, we show that the 5-th order ΔΣ D/A converter with the propose DAC achieves the S/N of 130 dB at the MOS transistor threshold voltage deviation of 100 mV.

KW - Data weighted averaging

KW - Digital-to-analog converter

KW - Multi delay inverter

KW - Pulse width modulation

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JF - IEEJ Transactions on Electronics, Information and Systems

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Multi bit PWMDAC with multi delay inverter

Abstract

Keywords

ASJC Scopus subject areas

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