Multi bit PWMDAC with multi delay inverter

Daichi Kodama, Eri Ioka, Yasuyuki Matsuya

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

The conventional local PWM-DAC for the ΔΣ D/A converter generates the PWM wave by dividing the clock signal. In this method, the sampling speed is decreased greatly by increasing the resolution. In this paper, we propose a new PWM-DAC with the Multi-Delay inverter. This DAC does not require the dividing clock as the conventional PWM-DAC. As simulation results, we show that the 5-th order ΔΣ D/A converter with the propose DAC achieves the S/N of 130 dB at the MOS transistor threshold voltage deviation of 100 mV.

Original languageEnglish
Pages (from-to)239-244
Number of pages6
JournalIEEJ Transactions on Electronics, Information and Systems
Volume133
Issue number2
DOIs
Publication statusPublished - 2013
Externally publishedYes

Fingerprint

Pulse width modulation
Clocks
MOSFET devices
Threshold voltage
Sampling

Keywords

  • Data weighted averaging
  • Digital-to-analog converter
  • Multi delay inverter
  • Pulse width modulation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Multi bit PWMDAC with multi delay inverter. / Kodama, Daichi; Ioka, Eri; Matsuya, Yasuyuki.

In: IEEJ Transactions on Electronics, Information and Systems, Vol. 133, No. 2, 2013, p. 239-244.

Research output: Contribution to journalArticle

Kodama, Daichi ; Ioka, Eri ; Matsuya, Yasuyuki. / Multi bit PWMDAC with multi delay inverter. In: IEEJ Transactions on Electronics, Information and Systems. 2013 ; Vol. 133, No. 2. pp. 239-244.
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