New frequency dependent target impedance for DDR3 memory system

Hayato Sasaki, Masato Kanazawa, Toshio Sudo, Atsushi Tomishima, Toshiyuki Kaneko

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Anti-resonance peak in power distribution network (PDN) impedance must be avoided to prevent the interference between signal integrity and power integrity of a system. Conventional criteria of PDN impedance is a target impedance with a constant value over wide frequency range. However, the constant target impedance is not suitable for the high-speed systems, such as DDR-3 memory systems, because it is not cost effective to maintain PDN impedance as low as possible, especially in high frequency range. Furthermore, clock frequencies of modern LSIs already exceed the peak frequency of PDN impedance. In this paper, frequency spectrum of the power supply switching current of the ASIC driver has been used to define the target impedance in the DDR3 memory system. Frequency dependent target impedance has been obtained from the switching current spectrum. Degradation of signal integrity, such as eye height and jitter due to anti-resonance peaks have been checked by comparing the frequency dependent target impedance of DDR3 system.

Original languageEnglish
Title of host publication2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
DOIs
Publication statusPublished - 2011
Event2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011 - Hanzhou
Duration: 2011 Dec 122011 Dec 14

Other

Other2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
CityHanzhou
Period11/12/1211/12/14

Fingerprint

Electric power distribution
Data storage equipment
Signal interference
Application specific integrated circuits
Jitter
Clocks
Degradation
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Sasaki, H., Kanazawa, M., Sudo, T., Tomishima, A., & Kaneko, T. (2011). New frequency dependent target impedance for DDR3 memory system. In 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011 [6213774] https://doi.org/10.1109/EDAPS.2011.6213774

New frequency dependent target impedance for DDR3 memory system. / Sasaki, Hayato; Kanazawa, Masato; Sudo, Toshio; Tomishima, Atsushi; Kaneko, Toshiyuki.

2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011. 2011. 6213774.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sasaki, H, Kanazawa, M, Sudo, T, Tomishima, A & Kaneko, T 2011, New frequency dependent target impedance for DDR3 memory system. in 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011., 6213774, 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011, Hanzhou, 11/12/12. https://doi.org/10.1109/EDAPS.2011.6213774
Sasaki H, Kanazawa M, Sudo T, Tomishima A, Kaneko T. New frequency dependent target impedance for DDR3 memory system. In 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011. 2011. 6213774 https://doi.org/10.1109/EDAPS.2011.6213774
Sasaki, Hayato ; Kanazawa, Masato ; Sudo, Toshio ; Tomishima, Atsushi ; Kaneko, Toshiyuki. / New frequency dependent target impedance for DDR3 memory system. 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011. 2011.
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