New silicon-on-insulator (SOI) flash memory with side channel and side floating gate

Hoon Choi; Tadao Tanabe; Noriyuki Kotaki; Kwang Wook Koh; Jeoung Chill Shim; Ki Tae Park; Hiroyuki Kurino; Mitsumasa Koyanagi

doi:10.1143/jjap.42.3361

New silicon-on-insulator (SOI) flash memory with side channel and side floating gate

Hoon Choi, Tadao Tanabe, Noriyuki Kotaki, Kwang Wook Koh, Jeoung Chill Shim, Ki Tae Park, Hiroyuki Kurino, Mitsumasa Koyanagi

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

A new silicon-on-insulator (SOI) flash memory with a side channel and side floating gate has been proposed to reduce the power consumption and to increase the packing density in this paper. We utilized atomic layer doping (ALD) method for forming the ultra shallow junction on the side surface of the device. The threshold voltage shift of 0.25 V was obtained for small erasing/writing voltages in a 0.1 μm SOI flash memory. This device can be operated with a small number of electrons.

Original language	English
Pages (from-to)	3361-3363
Number of pages	3
Journal	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume	42
Issue number	6 A
DOIs	https://doi.org/10.1143/jjap.42.3361
Publication status	Published - 2003 Jun
Externally published	Yes

Keywords

Atomic layer doping (ALD) method
Flash memory
Fowler Nordheim (FN) tunneling
Side channel
Silicon-on-insulator (SOI)

ASJC Scopus subject areas

Engineering(all)
Physics and Astronomy(all)

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10.1143/jjap.42.3361

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New silicon-on-insulator (SOI) flash memory with side channel and side floating gate. / Choi, Hoon; Tanabe, Tadao; Kotaki, Noriyuki; Koh, Kwang Wook; Shim, Jeoung Chill; Park, Ki Tae; Kurino, Hiroyuki; Koyanagi, Mitsumasa.

In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 42, No. 6 A, 06.2003, p. 3361-3363.

Research output: Contribution to journal › Article › peer-review

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abstract = "A new silicon-on-insulator (SOI) flash memory with a side channel and side floating gate has been proposed to reduce the power consumption and to increase the packing density in this paper. We utilized atomic layer doping (ALD) method for forming the ultra shallow junction on the side surface of the device. The threshold voltage shift of 0.25 V was obtained for small erasing/writing voltages in a 0.1 μm SOI flash memory. This device can be operated with a small number of electrons.",

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AU - Shim, Jeoung Chill

AU - Park, Ki Tae

AU - Kurino, Hiroyuki

AU - Koyanagi, Mitsumasa

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