New silicon-on-insulator (SOI) flash memory with side channel and side floating gate

Hoon Choi; Tadao Tanabe; Noriyuki Kotaki; Kwang Wook Koh; Jeoung Chill Shim; Ki Tae Park; Hiroyuki Kurino; Mitsumasa Koyanagi

doi:10.1143/jjap.42.3361

New silicon-on-insulator (SOI) flash memory with side channel and side floating gate

Hoon Choi, Tadao Tanabe, Noriyuki Kotaki, Kwang Wook Koh, Jeoung Chill Shim, Ki Tae Park, Hiroyuki Kurino, Mitsumasa Koyanagi

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

A new silicon-on-insulator (SOI) flash memory with a side channel and side floating gate has been proposed to reduce the power consumption and to increase the packing density in this paper. We utilized atomic layer doping (ALD) method for forming the ultra shallow junction on the side surface of the device. The threshold voltage shift of 0.25 V was obtained for small erasing/writing voltages in a 0.1 μm SOI flash memory. This device can be operated with a small number of electrons.

Original language	English
Pages (from-to)	3361-3363
Number of pages	3
Journal	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume	42
Issue number	6 A
DOIs	https://doi.org/10.1143/jjap.42.3361
Publication status	Published - 2003 Jun
Externally published	Yes

Keywords

Atomic layer doping (ALD) method
Flash memory
Fowler Nordheim (FN) tunneling
Side channel
Silicon-on-insulator (SOI)

ASJC Scopus subject areas

Engineering(all)
Physics and Astronomy(all)

Access to Document

10.1143/jjap.42.3361

Cite this

New silicon-on-insulator (SOI) flash memory with side channel and side floating gate. / Choi, Hoon; Tanabe, Tadao; Kotaki, Noriyuki; Koh, Kwang Wook; Shim, Jeoung Chill; Park, Ki Tae; Kurino, Hiroyuki; Koyanagi, Mitsumasa.

In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 42, No. 6 A, 06.2003, p. 3361-3363.

Research output: Contribution to journal › Article › peer-review

@article{1c73791f46074058bc10d66d6e4666fc,

title = "New silicon-on-insulator (SOI) flash memory with side channel and side floating gate",

abstract = "A new silicon-on-insulator (SOI) flash memory with a side channel and side floating gate has been proposed to reduce the power consumption and to increase the packing density in this paper. We utilized atomic layer doping (ALD) method for forming the ultra shallow junction on the side surface of the device. The threshold voltage shift of 0.25 V was obtained for small erasing/writing voltages in a 0.1 μm SOI flash memory. This device can be operated with a small number of electrons.",

keywords = "Atomic layer doping (ALD) method, Flash memory, Fowler Nordheim (FN) tunneling, Side channel, Silicon-on-insulator (SOI)",

author = "Hoon Choi and Tadao Tanabe and Noriyuki Kotaki and Koh, {Kwang Wook} and Shim, {Jeoung Chill} and Park, {Ki Tae} and Hiroyuki Kurino and Mitsumasa Koyanagi",

year = "2003",

month = jun,

doi = "10.1143/jjap.42.3361",

language = "English",

volume = "42",

pages = "3361--3363",

journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",

issn = "0021-4922",

publisher = "Japan Society of Applied Physics",

number = "6 A",

}

TY - JOUR

T1 - New silicon-on-insulator (SOI) flash memory with side channel and side floating gate

AU - Choi, Hoon

AU - Tanabe, Tadao

AU - Kotaki, Noriyuki

AU - Koh, Kwang Wook

AU - Shim, Jeoung Chill

AU - Park, Ki Tae

AU - Kurino, Hiroyuki

AU - Koyanagi, Mitsumasa

PY - 2003/6

Y1 - 2003/6

N2 - A new silicon-on-insulator (SOI) flash memory with a side channel and side floating gate has been proposed to reduce the power consumption and to increase the packing density in this paper. We utilized atomic layer doping (ALD) method for forming the ultra shallow junction on the side surface of the device. The threshold voltage shift of 0.25 V was obtained for small erasing/writing voltages in a 0.1 μm SOI flash memory. This device can be operated with a small number of electrons.

AB - A new silicon-on-insulator (SOI) flash memory with a side channel and side floating gate has been proposed to reduce the power consumption and to increase the packing density in this paper. We utilized atomic layer doping (ALD) method for forming the ultra shallow junction on the side surface of the device. The threshold voltage shift of 0.25 V was obtained for small erasing/writing voltages in a 0.1 μm SOI flash memory. This device can be operated with a small number of electrons.

KW - Atomic layer doping (ALD) method

KW - Flash memory

KW - Fowler Nordheim (FN) tunneling

KW - Side channel

KW - Silicon-on-insulator (SOI)

UR - http://www.scopus.com/inward/record.url?scp=0041379818&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0041379818&partnerID=8YFLogxK

U2 - 10.1143/jjap.42.3361

DO - 10.1143/jjap.42.3361

M3 - Article

AN - SCOPUS:0041379818

VL - 42

SP - 3361

EP - 3363

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 6 A

ER -

New silicon-on-insulator (SOI) flash memory with side channel and side floating gate

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this