Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Non-volatile power gating introducing MTJ into a flip-flop is an attractive technique for IoT devices. However, the time required for a successful store operation to MTJs varies at non-volatile flip-flops (NVFFs) due to process and voltage variation. This paper describes implementation and real-chip evaluation of a non-volatile Coarse Grained Reconfigurable Array employing verify-and-retryable NVFF (VR-NVFF) circuits and two-step store (TSS) control by instructions of a microcontroller. Test chips fabricated in a 40nm CMOS/MTJ hybrid technology have demonstrated that the TSS approach using both 30ns/100ns store operations reduces power by 37-42% when running an image processing program at 100MHz.

Original languageEnglish
Title of host publicationIEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728163475
DOIs
Publication statusPublished - 2020 Apr
Event23rd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Kokubunji, Japan
Duration: 2020 Apr 152020 Apr 17

Publication series

NameIEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings

Conference

Conference23rd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020
CountryJapan
CityKokubunji
Period20/4/1520/4/17

Keywords

  • Coarse Grained Reconfigurable Array
  • MTJ
  • Non-volatile
  • energy
  • flip-flop
  • power gating

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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