Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

Masaru Kudo, Kimiyoshi Usami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper describes an approach to combine spintransfer torque Magnetic Tunnel Junction (MTJ) based non-volatile flip-flops (NVFFs) with power gating techniques to enable anytime power-off and instant power-on. We analyzed the NVFFs which are expected to realize nonvolatile power gating (NVPG) for a microprocessor. We evaluated the NVFFs by the area, the performance and the energy dissipation. We also investigated effectiveness of NVPG that combines the NVFFs with the 32-bit microprocessor core. The simulation results showed that the NVPG reduced more energy dissipation when the idle time of the microprocessor is longer than 5ms at 25°C as compared with the conventional SRAM-backup scheme. Additionally, the NVPG was able to reduce more energy dissipation at higher temperature.

Original languageEnglish
Title of host publicationNVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538617687
DOIs
Publication statusPublished - 2017 Oct 10
Externally publishedYes
Event6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017 - Hsinchu, Taiwan, Province of China
Duration: 2017 Aug 162017 Aug 18

Other

Other6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017
CountryTaiwan, Province of China
CityHsinchu
Period17/8/1617/8/18

Fingerprint

Tunnel junctions
Flip flop circuits
Microprocessor chips
Energy dissipation
Static random access storage
Torque
Temperature

Keywords

  • Low Power
  • Magnetic Tunnel Junction
  • Nonvolatile Flip Flop
  • Power Gating

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Kudo, M., & Usami, K. (2017). Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. In NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium [8064472] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NVMSA.2017.8064472

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. / Kudo, Masaru; Usami, Kimiyoshi.

NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium. Institute of Electrical and Electronics Engineers Inc., 2017. 8064472.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kudo, M & Usami, K 2017, Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. in NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium., 8064472, Institute of Electrical and Electronics Engineers Inc., 6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017, Hsinchu, Taiwan, Province of China, 17/8/16. https://doi.org/10.1109/NVMSA.2017.8064472
Kudo M, Usami K. Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. In NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium. Institute of Electrical and Electronics Engineers Inc. 2017. 8064472 https://doi.org/10.1109/NVMSA.2017.8064472
Kudo, Masaru ; Usami, Kimiyoshi. / Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium. Institute of Electrical and Electronics Engineers Inc., 2017.
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