Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

Masaru Kudo, Kimiyoshi Usami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper describes an approach to combine spintransfer torque Magnetic Tunnel Junction (MTJ) based non-volatile flip-flops (NVFFs) with power gating techniques to enable anytime power-off and instant power-on. We analyzed the NVFFs which are expected to realize nonvolatile power gating (NVPG) for a microprocessor. We evaluated the NVFFs by the area, the performance and the energy dissipation. We also investigated effectiveness of NVPG that combines the NVFFs with the 32-bit microprocessor core. The simulation results showed that the NVPG reduced more energy dissipation when the idle time of the microprocessor is longer than 5ms at 25°C as compared with the conventional SRAM-backup scheme. Additionally, the NVPG was able to reduce more energy dissipation at higher temperature.

Original languageEnglish
Title of host publicationNVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538617687
DOIs
Publication statusPublished - 2017 Oct 10
Event6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017 - Hsinchu, Taiwan, Province of China
Duration: 2017 Aug 162017 Aug 18

Publication series

NameNVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium

Other

Other6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017
Country/TerritoryTaiwan, Province of China
CityHsinchu
Period17/8/1617/8/18

Keywords

  • Low Power
  • Magnetic Tunnel Junction
  • Nonvolatile Flip Flop
  • Power Gating

ASJC Scopus subject areas

  • Hardware and Architecture

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