TY - GEN
T1 - Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor
AU - Kudo, Masaru
AU - Usami, Kimiyoshi
PY - 2017/10/10
Y1 - 2017/10/10
N2 - This paper describes an approach to combine spintransfer torque Magnetic Tunnel Junction (MTJ) based non-volatile flip-flops (NVFFs) with power gating techniques to enable anytime power-off and instant power-on. We analyzed the NVFFs which are expected to realize nonvolatile power gating (NVPG) for a microprocessor. We evaluated the NVFFs by the area, the performance and the energy dissipation. We also investigated effectiveness of NVPG that combines the NVFFs with the 32-bit microprocessor core. The simulation results showed that the NVPG reduced more energy dissipation when the idle time of the microprocessor is longer than 5ms at 25°C as compared with the conventional SRAM-backup scheme. Additionally, the NVPG was able to reduce more energy dissipation at higher temperature.
AB - This paper describes an approach to combine spintransfer torque Magnetic Tunnel Junction (MTJ) based non-volatile flip-flops (NVFFs) with power gating techniques to enable anytime power-off and instant power-on. We analyzed the NVFFs which are expected to realize nonvolatile power gating (NVPG) for a microprocessor. We evaluated the NVFFs by the area, the performance and the energy dissipation. We also investigated effectiveness of NVPG that combines the NVFFs with the 32-bit microprocessor core. The simulation results showed that the NVPG reduced more energy dissipation when the idle time of the microprocessor is longer than 5ms at 25°C as compared with the conventional SRAM-backup scheme. Additionally, the NVPG was able to reduce more energy dissipation at higher temperature.
KW - Low Power
KW - Magnetic Tunnel Junction
KW - Nonvolatile Flip Flop
KW - Power Gating
UR - http://www.scopus.com/inward/record.url?scp=85034767209&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85034767209&partnerID=8YFLogxK
U2 - 10.1109/NVMSA.2017.8064472
DO - 10.1109/NVMSA.2017.8064472
M3 - Conference contribution
AN - SCOPUS:85034767209
T3 - NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium
BT - NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017
Y2 - 16 August 2017 through 18 August 2017
ER -