Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

Masaru Kudo; Kimiyoshi Usami

doi:10.1109/NVMSA.2017.8064472

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

Masaru Kudo, Kimiyoshi Usami

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

This paper describes an approach to combine spintransfer torque Magnetic Tunnel Junction (MTJ) based non-volatile flip-flops (NVFFs) with power gating techniques to enable anytime power-off and instant power-on. We analyzed the NVFFs which are expected to realize nonvolatile power gating (NVPG) for a microprocessor. We evaluated the NVFFs by the area, the performance and the energy dissipation. We also investigated effectiveness of NVPG that combines the NVFFs with the 32-bit microprocessor core. The simulation results showed that the NVPG reduced more energy dissipation when the idle time of the microprocessor is longer than 5ms at 25°C as compared with the conventional SRAM-backup scheme. Additionally, the NVPG was able to reduce more energy dissipation at higher temperature.

Original language	English
Title of host publication	NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538617687
DOIs	https://doi.org/10.1109/NVMSA.2017.8064472
Publication status	Published - 2017 Oct 10
Event	6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017 - Hsinchu, Taiwan, Province of China Duration: 2017 Aug 16 → 2017 Aug 18

Publication series

Name	NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium

Other

Other	6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	17/8/16 → 17/8/18

Keywords

Low Power
Magnetic Tunnel Junction
Nonvolatile Flip Flop
Power Gating

ASJC Scopus subject areas

Hardware and Architecture

Access to Document

10.1109/NVMSA.2017.8064472

Cite this

Kudo, M., & Usami, K. (2017). Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. In NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium [8064472] (NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NVMSA.2017.8064472

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. / Kudo, Masaru; Usami, Kimiyoshi.

NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium. Institute of Electrical and Electronics Engineers Inc., 2017. 8064472 (NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kudo, M & Usami, K 2017, Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. in NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium., 8064472, NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium, Institute of Electrical and Electronics Engineers Inc., 6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017, Hsinchu, Taiwan, Province of China, 17/8/16. https://doi.org/10.1109/NVMSA.2017.8064472

Kudo M, Usami K. Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. In NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium. Institute of Electrical and Electronics Engineers Inc. 2017. 8064472. (NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium). https://doi.org/10.1109/NVMSA.2017.8064472

@inproceedings{2014aa598d7040dabe1606f970042201,

title = "Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor",

abstract = "This paper describes an approach to combine spintransfer torque Magnetic Tunnel Junction (MTJ) based non-volatile flip-flops (NVFFs) with power gating techniques to enable anytime power-off and instant power-on. We analyzed the NVFFs which are expected to realize nonvolatile power gating (NVPG) for a microprocessor. We evaluated the NVFFs by the area, the performance and the energy dissipation. We also investigated effectiveness of NVPG that combines the NVFFs with the 32-bit microprocessor core. The simulation results showed that the NVPG reduced more energy dissipation when the idle time of the microprocessor is longer than 5ms at 25°C as compared with the conventional SRAM-backup scheme. Additionally, the NVPG was able to reduce more energy dissipation at higher temperature.",

keywords = "Low Power, Magnetic Tunnel Junction, Nonvolatile Flip Flop, Power Gating",

author = "Masaru Kudo and Kimiyoshi Usami",

year = "2017",

month = oct,

day = "10",

doi = "10.1109/NVMSA.2017.8064472",

language = "English",

series = "NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium",

note = "6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017 ; Conference date: 16-08-2017 Through 18-08-2017",

}

TY - GEN

T1 - Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

AU - Kudo, Masaru

AU - Usami, Kimiyoshi

PY - 2017/10/10

Y1 - 2017/10/10

N2 - This paper describes an approach to combine spintransfer torque Magnetic Tunnel Junction (MTJ) based non-volatile flip-flops (NVFFs) with power gating techniques to enable anytime power-off and instant power-on. We analyzed the NVFFs which are expected to realize nonvolatile power gating (NVPG) for a microprocessor. We evaluated the NVFFs by the area, the performance and the energy dissipation. We also investigated effectiveness of NVPG that combines the NVFFs with the 32-bit microprocessor core. The simulation results showed that the NVPG reduced more energy dissipation when the idle time of the microprocessor is longer than 5ms at 25°C as compared with the conventional SRAM-backup scheme. Additionally, the NVPG was able to reduce more energy dissipation at higher temperature.

AB - This paper describes an approach to combine spintransfer torque Magnetic Tunnel Junction (MTJ) based non-volatile flip-flops (NVFFs) with power gating techniques to enable anytime power-off and instant power-on. We analyzed the NVFFs which are expected to realize nonvolatile power gating (NVPG) for a microprocessor. We evaluated the NVFFs by the area, the performance and the energy dissipation. We also investigated effectiveness of NVPG that combines the NVFFs with the 32-bit microprocessor core. The simulation results showed that the NVPG reduced more energy dissipation when the idle time of the microprocessor is longer than 5ms at 25°C as compared with the conventional SRAM-backup scheme. Additionally, the NVPG was able to reduce more energy dissipation at higher temperature.

KW - Low Power

KW - Magnetic Tunnel Junction

KW - Nonvolatile Flip Flop

KW - Power Gating

UR - http://www.scopus.com/inward/record.url?scp=85034767209&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85034767209&partnerID=8YFLogxK

U2 - 10.1109/NVMSA.2017.8064472

DO - 10.1109/NVMSA.2017.8064472

M3 - Conference contribution

AN - SCOPUS:85034767209

T3 - NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium

BT - NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017

Y2 - 16 August 2017 through 18 August 2017

ER -

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this