Novel Viterbi decoder VLSI implementation and its performance

Shuji Kubota, Shuzo Kato, Tsunehachi Ishitani

Research output: Contribution to journalArticle

33 Citations (Scopus)

Abstract

This paper presents an advanced, high-speed, and universal-coding-rate Viterbi decoder VLSI implementation. Two novel circuit design schemes have been proposed: `scarce state transition (SST)' and `direct high-coding-rate convolutional code generation and variable-rate Viterbi decoding.' SST makes it possible to omit the final decision circuit and to reduce the required path memory length without degrading Pe performance. Moreover, the power consumption of the SST Viterbi decoder is significantly reduced when implemented as a CMOS devices. These features overcome the speed limits of high-speed and high-coding-gain Viterbi decoder VLSI's in the rate one-half mode imposed by the thermal limitation. Moreover, the proposed direct high-coding-rate convolutional code generation and variable-rate Viterbi decoding scheme make it possible to realize a simple and variable coding-rate forward-error-correction circuit by changing only the branch metric calculation ROM tables. By employing these schemes, high-speed (25 Mb/s) and universal-coding-rate Viterbi decoder VLSI's have been developed. Experimental results employing developed Viterbi decoder VLSI's confirm satisfactory Pe performance and high operation speeds under various conditions, for example, AWGN, cochannel interference, and adjacent channel interference environments.

Original languageEnglish
Pages (from-to)1170-1178
Number of pages9
JournalIEEE Transactions on Communications
Volume41
Issue number8
DOIs
Publication statusPublished - 1993 Aug
Externally publishedYes

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Convolutional codes
Decoding
Networks (circuits)
Cochannel interference
Forward error correction
ROM
Electric power utilization
Data storage equipment
Code generation
Hot Temperature

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Novel Viterbi decoder VLSI implementation and its performance. / Kubota, Shuji; Kato, Shuzo; Ishitani, Tsunehachi.

In: IEEE Transactions on Communications, Vol. 41, No. 8, 08.1993, p. 1170-1178.

Research output: Contribution to journalArticle

Kubota, Shuji ; Kato, Shuzo ; Ishitani, Tsunehachi. / Novel Viterbi decoder VLSI implementation and its performance. In: IEEE Transactions on Communications. 1993 ; Vol. 41, No. 8. pp. 1170-1178.
@article{fcb07c0b8a104bb79d088394b9122037,
title = "Novel Viterbi decoder VLSI implementation and its performance",
abstract = "This paper presents an advanced, high-speed, and universal-coding-rate Viterbi decoder VLSI implementation. Two novel circuit design schemes have been proposed: `scarce state transition (SST)' and `direct high-coding-rate convolutional code generation and variable-rate Viterbi decoding.' SST makes it possible to omit the final decision circuit and to reduce the required path memory length without degrading Pe performance. Moreover, the power consumption of the SST Viterbi decoder is significantly reduced when implemented as a CMOS devices. These features overcome the speed limits of high-speed and high-coding-gain Viterbi decoder VLSI's in the rate one-half mode imposed by the thermal limitation. Moreover, the proposed direct high-coding-rate convolutional code generation and variable-rate Viterbi decoding scheme make it possible to realize a simple and variable coding-rate forward-error-correction circuit by changing only the branch metric calculation ROM tables. By employing these schemes, high-speed (25 Mb/s) and universal-coding-rate Viterbi decoder VLSI's have been developed. Experimental results employing developed Viterbi decoder VLSI's confirm satisfactory Pe performance and high operation speeds under various conditions, for example, AWGN, cochannel interference, and adjacent channel interference environments.",
author = "Shuji Kubota and Shuzo Kato and Tsunehachi Ishitani",
year = "1993",
month = "8",
doi = "10.1109/26.231960",
language = "English",
volume = "41",
pages = "1170--1178",
journal = "IEEE Transactions on Communications",
issn = "0096-1965",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}

TY - JOUR

T1 - Novel Viterbi decoder VLSI implementation and its performance

AU - Kubota, Shuji

AU - Kato, Shuzo

AU - Ishitani, Tsunehachi

PY - 1993/8

Y1 - 1993/8

N2 - This paper presents an advanced, high-speed, and universal-coding-rate Viterbi decoder VLSI implementation. Two novel circuit design schemes have been proposed: `scarce state transition (SST)' and `direct high-coding-rate convolutional code generation and variable-rate Viterbi decoding.' SST makes it possible to omit the final decision circuit and to reduce the required path memory length without degrading Pe performance. Moreover, the power consumption of the SST Viterbi decoder is significantly reduced when implemented as a CMOS devices. These features overcome the speed limits of high-speed and high-coding-gain Viterbi decoder VLSI's in the rate one-half mode imposed by the thermal limitation. Moreover, the proposed direct high-coding-rate convolutional code generation and variable-rate Viterbi decoding scheme make it possible to realize a simple and variable coding-rate forward-error-correction circuit by changing only the branch metric calculation ROM tables. By employing these schemes, high-speed (25 Mb/s) and universal-coding-rate Viterbi decoder VLSI's have been developed. Experimental results employing developed Viterbi decoder VLSI's confirm satisfactory Pe performance and high operation speeds under various conditions, for example, AWGN, cochannel interference, and adjacent channel interference environments.

AB - This paper presents an advanced, high-speed, and universal-coding-rate Viterbi decoder VLSI implementation. Two novel circuit design schemes have been proposed: `scarce state transition (SST)' and `direct high-coding-rate convolutional code generation and variable-rate Viterbi decoding.' SST makes it possible to omit the final decision circuit and to reduce the required path memory length without degrading Pe performance. Moreover, the power consumption of the SST Viterbi decoder is significantly reduced when implemented as a CMOS devices. These features overcome the speed limits of high-speed and high-coding-gain Viterbi decoder VLSI's in the rate one-half mode imposed by the thermal limitation. Moreover, the proposed direct high-coding-rate convolutional code generation and variable-rate Viterbi decoding scheme make it possible to realize a simple and variable coding-rate forward-error-correction circuit by changing only the branch metric calculation ROM tables. By employing these schemes, high-speed (25 Mb/s) and universal-coding-rate Viterbi decoder VLSI's have been developed. Experimental results employing developed Viterbi decoder VLSI's confirm satisfactory Pe performance and high operation speeds under various conditions, for example, AWGN, cochannel interference, and adjacent channel interference environments.

UR - http://www.scopus.com/inward/record.url?scp=0027641448&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027641448&partnerID=8YFLogxK

U2 - 10.1109/26.231960

DO - 10.1109/26.231960

M3 - Article

VL - 41

SP - 1170

EP - 1178

JO - IEEE Transactions on Communications

JF - IEEE Transactions on Communications

SN - 0096-1965

IS - 8

ER -