Numerical analysis of GaAs MESFETs with p-buffer layer on semi-insulating substrate including deep traps

Kazushige Horio, H. Yanai

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Numerical analysis of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate is presented in which impurity compensation by traps is included. Using a p-buffer layer is shown to be effective in minimizing the short-channel effects as in the case of using a substrate with high density of traps.

Original languageEnglish
Pages (from-to)86-88
Number of pages3
JournalElectronics Letters
Volume25
Issue number2
Publication statusPublished - 1989 Jan 1

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Buffer layers
Numerical analysis
Substrates
Impurities
Compensation and Redress

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Numerical analysis of GaAs MESFETs with p-buffer layer on semi-insulating substrate including deep traps. / Horio, Kazushige; Yanai, H.

In: Electronics Letters, Vol. 25, No. 2, 01.01.1989, p. 86-88.

Research output: Contribution to journalArticle

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