Numerical Analysis of GaAs MESFETs with p-Buffer Layer on Semi-Insulating Substrate Including Deep TRAPS

K. Horio, H. Yanai

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Numerical analysis of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate is presented in which impurity compensation by traps is included. Using a p-buffer layer is shown to be effective in minimising the short-channel effects as in the case of using a substrate with high density of traps.

Original languageEnglish
Pages (from-to)86-88
Number of pages3
JournalElectronics Letters
Volume25
Issue number2
DOIs
Publication statusPublished - 1989 Sep 1

Keywords

  • FETs
  • Integrated circuits
  • Semiconductor devices and materials

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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