Numerical analysis of pulsed I-V curves and current collapse in GaN FETs as affected by buffer trapping

H. Nakano, H. Takayanagi, K. Yonemoto, Kazushige Horio

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Two-dimensional transient analysis of GaN MESFETs is performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. Quasi-pulsed I-V curves are derived from the transient characteristics, and are compared with the steady-state I-V curves. It is shown that so-called current collapse or current reduction is more pronounced when the deep-acceptor density in the buffer layer is higher and when an off-state drain voltage is higher, because the trapping effects become more significant. It is suggested that to minimize current collapse in GaN-based FETs, an acceptor density in a semi-insulating GaN layer should be made low, although the current cutoff behaviour may be degraded.

Original languageEnglish
Title of host publicationTechnical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
Pages141-144
Number of pages4
DOIs
Publication statusPublished - 2005
Event2005 IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC - Palm Springs, CA, United States
Duration: 2005 Oct 302005 Nov 2

Other

Other2005 IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
CountryUnited States
CityPalm Springs, CA
Period05/10/3005/11/2

Fingerprint

Buffer layers
Field effect transistors
Numerical analysis
Transient analysis
Electric potential
Compensation and Redress

Keywords

  • Current collapse
  • Deep level
  • Device simulation
  • FET
  • GaN

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Nakano, H., Takayanagi, H., Yonemoto, K., & Horio, K. (2005). Numerical analysis of pulsed I-V curves and current collapse in GaN FETs as affected by buffer trapping. In Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC (pp. 141-144). [H.2] https://doi.org/10.1109/CSICS.2005.1531789

Numerical analysis of pulsed I-V curves and current collapse in GaN FETs as affected by buffer trapping. / Nakano, H.; Takayanagi, H.; Yonemoto, K.; Horio, Kazushige.

Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC. 2005. p. 141-144 H.2.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nakano, H, Takayanagi, H, Yonemoto, K & Horio, K 2005, Numerical analysis of pulsed I-V curves and current collapse in GaN FETs as affected by buffer trapping. in Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC., H.2, pp. 141-144, 2005 IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC, Palm Springs, CA, United States, 05/10/30. https://doi.org/10.1109/CSICS.2005.1531789
Nakano H, Takayanagi H, Yonemoto K, Horio K. Numerical analysis of pulsed I-V curves and current collapse in GaN FETs as affected by buffer trapping. In Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC. 2005. p. 141-144. H.2 https://doi.org/10.1109/CSICS.2005.1531789
Nakano, H. ; Takayanagi, H. ; Yonemoto, K. ; Horio, Kazushige. / Numerical analysis of pulsed I-V curves and current collapse in GaN FETs as affected by buffer trapping. Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC. 2005. pp. 141-144
@inproceedings{1e005a7420674bf595629729198b1458,
title = "Numerical analysis of pulsed I-V curves and current collapse in GaN FETs as affected by buffer trapping",
abstract = "Two-dimensional transient analysis of GaN MESFETs is performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. Quasi-pulsed I-V curves are derived from the transient characteristics, and are compared with the steady-state I-V curves. It is shown that so-called current collapse or current reduction is more pronounced when the deep-acceptor density in the buffer layer is higher and when an off-state drain voltage is higher, because the trapping effects become more significant. It is suggested that to minimize current collapse in GaN-based FETs, an acceptor density in a semi-insulating GaN layer should be made low, although the current cutoff behaviour may be degraded.",
keywords = "Current collapse, Deep level, Device simulation, FET, GaN",
author = "H. Nakano and H. Takayanagi and K. Yonemoto and Kazushige Horio",
year = "2005",
doi = "10.1109/CSICS.2005.1531789",
language = "English",
pages = "141--144",
booktitle = "Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC",

}

TY - GEN

T1 - Numerical analysis of pulsed I-V curves and current collapse in GaN FETs as affected by buffer trapping

AU - Nakano, H.

AU - Takayanagi, H.

AU - Yonemoto, K.

AU - Horio, Kazushige

PY - 2005

Y1 - 2005

N2 - Two-dimensional transient analysis of GaN MESFETs is performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. Quasi-pulsed I-V curves are derived from the transient characteristics, and are compared with the steady-state I-V curves. It is shown that so-called current collapse or current reduction is more pronounced when the deep-acceptor density in the buffer layer is higher and when an off-state drain voltage is higher, because the trapping effects become more significant. It is suggested that to minimize current collapse in GaN-based FETs, an acceptor density in a semi-insulating GaN layer should be made low, although the current cutoff behaviour may be degraded.

AB - Two-dimensional transient analysis of GaN MESFETs is performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. Quasi-pulsed I-V curves are derived from the transient characteristics, and are compared with the steady-state I-V curves. It is shown that so-called current collapse or current reduction is more pronounced when the deep-acceptor density in the buffer layer is higher and when an off-state drain voltage is higher, because the trapping effects become more significant. It is suggested that to minimize current collapse in GaN-based FETs, an acceptor density in a semi-insulating GaN layer should be made low, although the current cutoff behaviour may be degraded.

KW - Current collapse

KW - Deep level

KW - Device simulation

KW - FET

KW - GaN

UR - http://www.scopus.com/inward/record.url?scp=30944453534&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=30944453534&partnerID=8YFLogxK

U2 - 10.1109/CSICS.2005.1531789

DO - 10.1109/CSICS.2005.1531789

M3 - Conference contribution

SP - 141

EP - 144

BT - Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC

ER -