Numerical simulation of GaAs MESFET's with a p-buffer layer on the semi-insulating substrate compensated by deep traps

Kazushige Horio, Yasuji Fuseya, Hiroyuki Kusuki, Hisayoshi Yanai

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A numerical analysis of GaAs MESFETs with a p-buffer layer on a semi-insulating substrate is performed in which impurity compensation by traps in the substrate is considered. It is shown that the use of a thick p-buffer layer results in a lower device current due to the formation of a steep barrier at the channel-substrate interface. It is also shown that with higher trap and acceptor densities in the substrate, the drain current becomes lower due to the decrease in the substrate current. This decrease occurs because a negative-space-charge layer is formed in the substrate. It is demonstrated that when the p-buffer layer is fully depleted, its acceptors play the same electrical role as the acceptors within the space-charge region of the semi-insulating substrate. Thus, using a thick p-buffer layer has the same effect as using a substrate with a high density of traps, i.e., it minimizes the short-channel effects in GaAs MESFETs. Therefore, if the trap density in the substrate is low, the short-channel effects can be reduced by introducing a p-buffer layer or a buried p-layer.

Original languageEnglish
Pages (from-to)1371-1379
Number of pages9
JournalIEEE Transactions on Microwave Theory and Techniques
Issue number9
Publication statusPublished - 1989 Sep
Externally publishedYes


ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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