Numerical simulation of GaAs MESFET's with heavily compensated substrates.

Kazushige Horio, H. Yanai, T. Ikoma

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The authors describe numerical simulations of GaAs MESFETs (metal-semiconductor field-effect transistors) on a semi-insulating substrate in which impurities are compensated by deep traps. It is shown that higher acceptor density in the substrate results in lower device current due to the formation of a space-charge layer at the channel-substrate interface. It is also shown that drain currents increase continuously because electrons are injected to fill the traps in the substrate and a current path through the substrate is formed. This substrate current becomes pronounced for shorter-gate-length MESFETs on a substrate with lower impurity densities. It is suggested that to minimize short-channel effects in GaAs MESFETs, impurity densities in the semi-insulating substrate must be high.

Original languageEnglish
Title of host publicationNASECODE V Proc Fifth Int Conf Numer Anal Semicond Devices Integr Circuit
EditorsJ.J.H. Miller
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Pages237-242
Number of pages6
ISBN (Print)0906783720
Publication statusPublished - 1987
EventNASECODE V: Proceedings of the Fifth International Conference on the Numerical Analysis of Semiconductor Devices and Integrated Circuits - Dublin, Ireland
Duration: 1987 Jun 171987 Jun 19

Other

OtherNASECODE V: Proceedings of the Fifth International Conference on the Numerical Analysis of Semiconductor Devices and Integrated Circuits
CityDublin, Ireland
Period87/6/1787/6/19

Fingerprint

Computer simulation
MESFET devices
Substrates
Impurities
Drain current
Electric space charge
Electrons

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Horio, K., Yanai, H., & Ikoma, T. (1987). Numerical simulation of GaAs MESFET's with heavily compensated substrates. In J. J. H. Miller (Ed.), NASECODE V Proc Fifth Int Conf Numer Anal Semicond Devices Integr Circuit (pp. 237-242). Piscataway, NJ, United States: Publ by IEEE.

Numerical simulation of GaAs MESFET's with heavily compensated substrates. / Horio, Kazushige; Yanai, H.; Ikoma, T.

NASECODE V Proc Fifth Int Conf Numer Anal Semicond Devices Integr Circuit. ed. / J.J.H. Miller. Piscataway, NJ, United States : Publ by IEEE, 1987. p. 237-242.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Horio, K, Yanai, H & Ikoma, T 1987, Numerical simulation of GaAs MESFET's with heavily compensated substrates. in JJH Miller (ed.), NASECODE V Proc Fifth Int Conf Numer Anal Semicond Devices Integr Circuit. Publ by IEEE, Piscataway, NJ, United States, pp. 237-242, NASECODE V: Proceedings of the Fifth International Conference on the Numerical Analysis of Semiconductor Devices and Integrated Circuits, Dublin, Ireland, 87/6/17.
Horio K, Yanai H, Ikoma T. Numerical simulation of GaAs MESFET's with heavily compensated substrates. In Miller JJH, editor, NASECODE V Proc Fifth Int Conf Numer Anal Semicond Devices Integr Circuit. Piscataway, NJ, United States: Publ by IEEE. 1987. p. 237-242
Horio, Kazushige ; Yanai, H. ; Ikoma, T. / Numerical simulation of GaAs MESFET's with heavily compensated substrates. NASECODE V Proc Fifth Int Conf Numer Anal Semicond Devices Integr Circuit. editor / J.J.H. Miller. Piscataway, NJ, United States : Publ by IEEE, 1987. pp. 237-242
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