On-chip detection methodology for break-even time of power gated function units

Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the minimum required time i.e. the break-even time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.

Original languageEnglish
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design
Pages241-246
Number of pages6
DOIs
Publication statusPublished - 2011
Event17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka
Duration: 2011 Aug 12011 Aug 3

Other

Other17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
CityFukuoka
Period11/8/111/8/3

Fingerprint

Program processors
Energy conservation
Switches
Networks (circuits)
Temperature

Keywords

  • break-even time
  • leakage monitor
  • power gating

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H., & Nakamura, H. (2011). On-chip detection methodology for break-even time of power gated function units. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 241-246). [5993643] https://doi.org/10.1109/ISLPED.2011.5993643

On-chip detection methodology for break-even time of power gated function units. / Usami, Kimiyoshi; Goto, Yuya; Matsunaga, Kensaku; Koyama, Satoshi; Ikebuchi, Daisuke; Amano, Hideharu; Nakamura, Hiroshi.

Proceedings of the International Symposium on Low Power Electronics and Design. 2011. p. 241-246 5993643.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Usami, K, Goto, Y, Matsunaga, K, Koyama, S, Ikebuchi, D, Amano, H & Nakamura, H 2011, On-chip detection methodology for break-even time of power gated function units. in Proceedings of the International Symposium on Low Power Electronics and Design., 5993643, pp. 241-246, 17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011, Fukuoka, 11/8/1. https://doi.org/10.1109/ISLPED.2011.5993643
Usami K, Goto Y, Matsunaga K, Koyama S, Ikebuchi D, Amano H et al. On-chip detection methodology for break-even time of power gated function units. In Proceedings of the International Symposium on Low Power Electronics and Design. 2011. p. 241-246. 5993643 https://doi.org/10.1109/ISLPED.2011.5993643
Usami, Kimiyoshi ; Goto, Yuya ; Matsunaga, Kensaku ; Koyama, Satoshi ; Ikebuchi, Daisuke ; Amano, Hideharu ; Nakamura, Hiroshi. / On-chip detection methodology for break-even time of power gated function units. Proceedings of the International Symposium on Low Power Electronics and Design. 2011. pp. 241-246
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