On-chip power integrity evaluation system

Yoshitaka Nabeshima, Yoshiaki Oizono, Takafumi Okumura, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Power supply disturbance excited by simultaneous switching output (SSO) circuits or core circuits is a serious issue in a system-in-package (SIP), especially in 3D stacked die package, because much more I/O circuits and core circuits excited simultaneously in synchronized with clock edges than the case of single die package. Therefore, decoupling schemes in such SiP's must be carefully designed including on-chip capacitance as well as off-chip capacitance so as to reduce the impedance of power distribution network (PDN) as low as possible up to high frequency range. In this paper, an on-chip power integrity evaluation system has been established using a test chip with both noise generating circuits and monitoring circuits for on-chip power supply noise. On-chip power integrity has been examined and compared for the cases with and without on-chip capacitance and for the various embedded capacitors inside an interposer.

Original languageEnglish
Title of host publicationProceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011
Pages165-169
Number of pages5
Publication statusPublished - 2011
Event8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2011 - Dubrovnik
Duration: 2011 Nov 62011 Nov 9

Other

Other8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2011
CityDubrovnik
Period11/11/611/11/9

Fingerprint

Networks (circuits)
Capacitance
Electric power distribution
Clocks
Capacitors
Monitoring
System-in-package

Keywords

  • interposer
  • On-chip Power Integrity
  • power distribution network
  • Power supply disturbance
  • system-in-package

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Nabeshima, Y., Oizono, Y., Okumura, T., & Sudo, T. (2011). On-chip power integrity evaluation system. In Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011 (pp. 165-169). [6130087]

On-chip power integrity evaluation system. / Nabeshima, Yoshitaka; Oizono, Yoshiaki; Okumura, Takafumi; Sudo, Toshio.

Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011. 2011. p. 165-169 6130087.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nabeshima, Y, Oizono, Y, Okumura, T & Sudo, T 2011, On-chip power integrity evaluation system. in Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011., 6130087, pp. 165-169, 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2011, Dubrovnik, 11/11/6.
Nabeshima Y, Oizono Y, Okumura T, Sudo T. On-chip power integrity evaluation system. In Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011. 2011. p. 165-169. 6130087
Nabeshima, Yoshitaka ; Oizono, Yoshiaki ; Okumura, Takafumi ; Sudo, Toshio. / On-chip power integrity evaluation system. Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011. 2011. pp. 165-169
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