On-die PDN design and analysis for minimizing power supply noise

Hiroki Otsuka, Genki Kubo, Ryota Kobayashi, Tatsuya Mido, Yoshinori Kobayashi, Hideyuki Fujii, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Power integrity design is a critical issue for advanced CMOS LSIs which operate at higher clock frequency and at lower supply voltage. Power supply fluctuation excited by core circuits or I/O buffer circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be designed as low as possible in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN created by the parallel combination of on-chip capacitance and package inductance induce the unwanted power supply fluctuation. In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adjusting different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions. The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.

Original languageEnglish
Title of host publication2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
Pages17-20
Number of pages4
DOIs
Publication statusPublished - 2012
Event2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 - Taipei
Duration: 2012 Dec 92012 Dec 11

Other

Other2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
CityTaipei
Period12/12/912/12/11

Fingerprint

Electric power distribution
Buffer circuits
Damping
Inductance
Electromagnetic waves
Clocks
Capacitance
Networks (circuits)
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Otsuka, H., Kubo, G., Kobayashi, R., Mido, T., Kobayashi, Y., Fujii, H., & Sudo, T. (2012). On-die PDN design and analysis for minimizing power supply noise. In 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 (pp. 17-20). [6469418] https://doi.org/10.1109/EDAPS.2012.6469418

On-die PDN design and analysis for minimizing power supply noise. / Otsuka, Hiroki; Kubo, Genki; Kobayashi, Ryota; Mido, Tatsuya; Kobayashi, Yoshinori; Fujii, Hideyuki; Sudo, Toshio.

2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. p. 17-20 6469418.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Otsuka, H, Kubo, G, Kobayashi, R, Mido, T, Kobayashi, Y, Fujii, H & Sudo, T 2012, On-die PDN design and analysis for minimizing power supply noise. in 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012., 6469418, pp. 17-20, 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012, Taipei, 12/12/9. https://doi.org/10.1109/EDAPS.2012.6469418
Otsuka H, Kubo G, Kobayashi R, Mido T, Kobayashi Y, Fujii H et al. On-die PDN design and analysis for minimizing power supply noise. In 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. p. 17-20. 6469418 https://doi.org/10.1109/EDAPS.2012.6469418
Otsuka, Hiroki ; Kubo, Genki ; Kobayashi, Ryota ; Mido, Tatsuya ; Kobayashi, Yoshinori ; Fujii, Hideyuki ; Sudo, Toshio. / On-die PDN design and analysis for minimizing power supply noise. 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. pp. 17-20
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