Based on a real open loop architecture and a cascode-driver CMOS source-follower, we implemented a S/H circuit in a 0.8 μm digital CMOS process. The circuit achieved -61 dB THD at a sampling rate of 103 MHz, while a 1.42 Vp-p 10 MHz input signal was applied. This includes all parasitic loading and transient effect.
|Number of pages||3|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|Publication status||Published - 1998 Jan 1|
|Event||Proceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA|
Duration: 1998 May 11 → 1998 May 14
ASJC Scopus subject areas
- Electrical and Electronic Engineering