Open-loop full CMOS 103 MHz -61 dB THD S/H circuit

Khayrollah Hadidi, Masahiro Sasaki, Tadatoshi Watanabe, Daigo Muramatsu, Takashi Matsumoto

Research output: Contribution to journalConference articlepeer-review

19 Citations (Scopus)

Abstract

Based on a real open loop architecture and a cascode-driver CMOS source-follower, we implemented a S/H circuit in a 0.8 μm digital CMOS process. The circuit achieved -61 dB THD at a sampling rate of 103 MHz, while a 1.42 Vp-p 10 MHz input signal was applied. This includes all parasitic loading and transient effect.

Original languageEnglish
Pages (from-to)381-383
Number of pages3
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 1998 Jan 1
EventProceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: 1998 May 111998 May 14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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