Optimal Design for Level-Shifter-Less Approach Using Channel Length Modulation Body Biasing

Tatsuya Watanabe, Kimiyoshi Usami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A multi-VDD design realizes LSIs to be low power by allowing to use multiple different power supply voltages. In this design, conversion of the voltage amplitude of the signal is necessary. This is usually done by inserting a circuit called a level shifter, between voltage domains as an interface. However, insertion of level shifter has disadvantages in silicon footprint, power consumption, and delays. In this paper, we propose a level-shifter-less approach by increasing channel length. We also propose the optimal design using both channel length modulation and body biasing.

Original languageEnglish
Title of host publicationITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages223-227
Number of pages5
ISBN (Electronic)9784885523281
Publication statusPublished - 2020 Jul
Event35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020 - Nagoya, Japan
Duration: 2020 Jul 32020 Jul 6

Publication series

NameITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications

Conference

Conference35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020
CountryJapan
CityNagoya
Period20/7/320/7/6

Keywords

  • Body Biasing
  • Channel Length Modulation
  • Level-Shifter-Less

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Information Systems and Management
  • Electrical and Electronic Engineering

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