Optimized design method for full-custom microprocessors

Kimiyoshi Usami; Jun Iwamura

doi:10.1109/CICC.1989.56790

Optimized design method for full-custom microprocessors

Kimiyoshi Usami, Jun Iwamura

Research output: Contribution to journal › Conference article › peer-review

1 Citation (Scopus)

Abstract

An effective design method for VLSI-based microprocessors is proposed. According to the method, the chip is divided into three categories; control logics, datapaths and macrocells at the very early stage. The control logics are automatically designed by a logic synthesis and an automatic placement & routing. For the datapaths and the macrocells, logic and layout are designed manually. By combining the design method with "design-pipelining", a 32-bit microprocessor including 460K transistors was designed in a year without sacrificing the chip size and the performance. An impact on design effort is also discussed.

Original language	English
Article number	5726257
Pages (from-to)	19.5.1-19.5.5
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.1989.56790
Publication status	Published - 1989 Dec 1
Externally published	Yes
Event	11th IEEE 1989 Custom Integrated Circuits Conference, CICC'89 - San Diego, CA, United States Duration: 1989 May 15 → 1989 May 18

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.1989.56790

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Cite this

@article{5852bbd4b5a842b598c5040580a6a386,

title = "Optimized design method for full-custom microprocessors",

abstract = "An effective design method for VLSI-based microprocessors is proposed. According to the method, the chip is divided into three categories; control logics, datapaths and macrocells at the very early stage. The control logics are automatically designed by a logic synthesis and an automatic placement & routing. For the datapaths and the macrocells, logic and layout are designed manually. By combining the design method with {"}design-pipelining{"}, a 32-bit microprocessor including 460K transistors was designed in a year without sacrificing the chip size and the performance. An impact on design effort is also discussed.",

author = "Kimiyoshi Usami and Jun Iwamura",

year = "1989",

month = dec,

day = "1",

doi = "10.1109/CICC.1989.56790",

language = "English",

pages = "19.5.1--19.5.5",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "11th IEEE 1989 Custom Integrated Circuits Conference, CICC'89 ; Conference date: 15-05-1989 Through 18-05-1989",

}

TY - JOUR

T1 - Optimized design method for full-custom microprocessors

AU - Usami, Kimiyoshi

AU - Iwamura, Jun

PY - 1989/12/1

Y1 - 1989/12/1

N2 - An effective design method for VLSI-based microprocessors is proposed. According to the method, the chip is divided into three categories; control logics, datapaths and macrocells at the very early stage. The control logics are automatically designed by a logic synthesis and an automatic placement & routing. For the datapaths and the macrocells, logic and layout are designed manually. By combining the design method with "design-pipelining", a 32-bit microprocessor including 460K transistors was designed in a year without sacrificing the chip size and the performance. An impact on design effort is also discussed.

AB - An effective design method for VLSI-based microprocessors is proposed. According to the method, the chip is divided into three categories; control logics, datapaths and macrocells at the very early stage. The control logics are automatically designed by a logic synthesis and an automatic placement & routing. For the datapaths and the macrocells, logic and layout are designed manually. By combining the design method with "design-pipelining", a 32-bit microprocessor including 460K transistors was designed in a year without sacrificing the chip size and the performance. An impact on design effort is also discussed.

UR - http://www.scopus.com/inward/record.url?scp=0024663230&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024663230&partnerID=8YFLogxK

U2 - 10.1109/CICC.1989.56790

DO - 10.1109/CICC.1989.56790

M3 - Conference article

AN - SCOPUS:0024663230

SP - 19.5.1-19.5.5

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

SN - 0886-5930

M1 - 5726257

T2 - 11th IEEE 1989 Custom Integrated Circuits Conference, CICC'89

Y2 - 15 May 1989 through 18 May 1989

ER -