PACKAGING TECHNOLOGY FOR HIGH SPEED LOGIC DEVICES.

T. Sudo, A. Iida, K. Yoshihara, T. Miyagi, T. Saito

Research output: Contribution to conferencePaper

Abstract

Recent advances in high speed logic ICs have given rise to the need for a new concept in packaging technology. High speed devices such as GaAs digital ICs are expected to operate in high speed and relatively low power dissipation. The authors discuss internal gate-to-gate interconnection wiring energy and external chip-to-chip interconnection energy. GaAs digital ICs have high output impedance, so the high characteristic impedance of transmission lines on the packaging substrate would be advantageous in reducing chip-to-chip interconnection energy and preserving inherent chip speed. On the other hand, the crosstalk induced between adjacent lines becomes greater, so that the optimum condition of the interconnection structure on the packaging substrate will be determined as a tradeoff between the above two factors.

Original languageEnglish
Pages160-164
Number of pages5
Publication statusPublished - 1984 Dec 1

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Sudo, T., Iida, A., Yoshihara, K., Miyagi, T., & Saito, T. (1984). PACKAGING TECHNOLOGY FOR HIGH SPEED LOGIC DEVICES.. 160-164.