PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations

Atsushi Sakai, Shigeru Yamada, Takashi Kariya, Shiro Uchiyama, Hiroaki Ikeda, Haruya Fujita, Hiroki Takatani, Yosuke Tanaka, Yoshiaki Oizono, Yoshitaka Nabeshima, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The 4096 bits wide-bus three-dimensional integration device using through-silicon-vias (TSVs) has been designed and fabricated as a demonstrator for power integrity such as power distribution network (PDN) impedance and simultaneous switching output (SSO) noise characteristics. Anti-resonance peak of total PDN impedance was extracted at around 80 MHz. This result was well coincident with maximum SSO noise frequency at around 75 MHz. Further, SSO noise reduction clocking named phase-shift clock has also been implemented to demonstrate the effectiveness as measurement basis.

Original languageEnglish
Title of host publication2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012 - Kyoto, Japan
Duration: 2012 Dec 102012 Dec 12

Publication series

Name2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012

Conference

Conference2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
CountryJapan
CityKyoto
Period12/12/1012/12/12

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Sakai, A., Yamada, S., Kariya, T., Uchiyama, S., Ikeda, H., Fujita, H., Takatani, H., Tanaka, Y., Oizono, Y., Nabeshima, Y., & Sudo, T. (2012). PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations. In 2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012 [6523460] (2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012). https://doi.org/10.1109/ICSJ.2012.6523460