PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations

Atsushi Sakai; Shigeru Yamada; Takashi Kariya; Shiro Uchiyama; Hiroaki Ikeda; Haruya Fujita; Hiroki Takatani; Yosuke Tanaka; Yoshiaki Oizono; Yoshitaka Nabeshima; Toshio Sudo

doi:10.1109/ICSJ.2012.6523460

PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations

Atsushi Sakai, Shigeru Yamada, Takashi Kariya, Shiro Uchiyama, Hiroaki Ikeda, Haruya Fujita, Hiroki Takatani, Yosuke Tanaka, Yoshiaki Oizono, Yoshitaka Nabeshima, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

The 4096 bits wide-bus three-dimensional integration device using through-silicon-vias (TSVs) has been designed and fabricated as a demonstrator for power integrity such as power distribution network (PDN) impedance and simultaneous switching output (SSO) noise characteristics. Anti-resonance peak of total PDN impedance was extracted at around 80 MHz. This result was well coincident with maximum SSO noise frequency at around 75 MHz. Further, SSO noise reduction clocking named phase-shift clock has also been implemented to demonstrate the effectiveness as measurement basis.

Original language	English
Title of host publication	2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
DOIs	https://doi.org/10.1109/ICSJ.2012.6523460
Publication status	Published - 2012 Dec 1
Event	2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012 - Kyoto, Japan Duration: 2012 Dec 10 → 2012 Dec 12

Publication series

Name	2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012

Conference

Conference	2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
Country/Territory	Japan
City	Kyoto
Period	12/12/10 → 12/12/12

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ICSJ.2012.6523460

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Sakai, A., Yamada, S., Kariya, T., Uchiyama, S., Ikeda, H., Fujita, H., Takatani, H., Tanaka, Y., Oizono, Y., Nabeshima, Y., & Sudo, T. (2012). PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations. In 2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012 [6523460] (2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012). https://doi.org/10.1109/ICSJ.2012.6523460

Sakai, A, Yamada, S, Kariya, T, Uchiyama, S, Ikeda, H, Fujita, H, Takatani, H, Tanaka, Y, Oizono, Y, Nabeshima, Y & Sudo, T 2012, PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations. in 2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012., 6523460, 2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012, 2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012, Kyoto, Japan, 12/12/10. https://doi.org/10.1109/ICSJ.2012.6523460

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title = "PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations",

abstract = "The 4096 bits wide-bus three-dimensional integration device using through-silicon-vias (TSVs) has been designed and fabricated as a demonstrator for power integrity such as power distribution network (PDN) impedance and simultaneous switching output (SSO) noise characteristics. Anti-resonance peak of total PDN impedance was extracted at around 80 MHz. This result was well coincident with maximum SSO noise frequency at around 75 MHz. Further, SSO noise reduction clocking named phase-shift clock has also been implemented to demonstrate the effectiveness as measurement basis.",

author = "Atsushi Sakai and Shigeru Yamada and Takashi Kariya and Shiro Uchiyama and Hiroaki Ikeda and Haruya Fujita and Hiroki Takatani and Yosuke Tanaka and Yoshiaki Oizono and Yoshitaka Nabeshima and Toshio Sudo",

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doi = "10.1109/ICSJ.2012.6523460",

language = "English",

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series = "2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012",

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T1 - PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations

AU - Sakai, Atsushi

AU - Yamada, Shigeru

AU - Kariya, Takashi

AU - Uchiyama, Shiro

AU - Ikeda, Hiroaki

AU - Fujita, Haruya

AU - Takatani, Hiroki

AU - Tanaka, Yosuke

AU - Oizono, Yoshiaki

AU - Nabeshima, Yoshitaka

AU - Sudo, Toshio

PY - 2012/12/1

Y1 - 2012/12/1

N2 - The 4096 bits wide-bus three-dimensional integration device using through-silicon-vias (TSVs) has been designed and fabricated as a demonstrator for power integrity such as power distribution network (PDN) impedance and simultaneous switching output (SSO) noise characteristics. Anti-resonance peak of total PDN impedance was extracted at around 80 MHz. This result was well coincident with maximum SSO noise frequency at around 75 MHz. Further, SSO noise reduction clocking named phase-shift clock has also been implemented to demonstrate the effectiveness as measurement basis.

AB - The 4096 bits wide-bus three-dimensional integration device using through-silicon-vias (TSVs) has been designed and fabricated as a demonstrator for power integrity such as power distribution network (PDN) impedance and simultaneous switching output (SSO) noise characteristics. Anti-resonance peak of total PDN impedance was extracted at around 80 MHz. This result was well coincident with maximum SSO noise frequency at around 75 MHz. Further, SSO noise reduction clocking named phase-shift clock has also been implemented to demonstrate the effectiveness as measurement basis.

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T3 - 2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012

BT - 2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012

T2 - 2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012

Y2 - 10 December 2012 through 12 December 2012

ER -

PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations

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