PDN impedance and noise simulation of 3D SiP with a widebus structure

Hiroki Takatani, Yosuke Tanaka, Yoshiaki Oizono, Yoshitaka Nabeshima, Takafumi Okumura, Toshio Sudo, Atsushi Sakai, Shiro Uchiyama, Hiroaki Ikeda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

A 3D stacked system-in-package (SiP) with a widebus structure is expected to have large SSO noise compared with conventional memory devices with small number of IOs. Then, Power supply impedances for a 3D SiP with a widebus structure has been investigated including stacked chips, an organic substrate, and a board. The 3D SiP consisted of 3 stacked chips and an organic substrate. These three chips were a memory chip on the top, a silicon interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer. Next, these 3 stacked chips were assembled on the organic substrate, whose size was 26 mm by 26mm. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.) and confirmed by measurement. Then, the PDN impedance for the organic substrate was extracted by using SIwave (Ansys Inc.) and also confirmed by measurement. Finally, the total PDN impedance seen from each chip was synthesized to estimate the power supply disturbance due to the anti-resonance peak, and power supply noise level was estimated by establishing a whole SPICE model.

Original languageEnglish
Title of host publicationProceedings - Electronic Components and Technology Conference
Pages673-677
Number of pages5
DOIs
Publication statusPublished - 2012
Event2012 IEEE 62nd Electronic Components and Technology Conference, ECTC 2012 - San Diego, CA
Duration: 2012 May 292012 Jun 1

Other

Other2012 IEEE 62nd Electronic Components and Technology Conference, ECTC 2012
CitySan Diego, CA
Period12/5/2912/6/1

Fingerprint

Silicon
Substrates
Data storage equipment
SPICE
Printed circuit boards
System-in-package

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Takatani, H., Tanaka, Y., Oizono, Y., Nabeshima, Y., Okumura, T., Sudo, T., ... Ikeda, H. (2012). PDN impedance and noise simulation of 3D SiP with a widebus structure. In Proceedings - Electronic Components and Technology Conference (pp. 673-677). [6248904] https://doi.org/10.1109/ECTC.2012.6248904

PDN impedance and noise simulation of 3D SiP with a widebus structure. / Takatani, Hiroki; Tanaka, Yosuke; Oizono, Yoshiaki; Nabeshima, Yoshitaka; Okumura, Takafumi; Sudo, Toshio; Sakai, Atsushi; Uchiyama, Shiro; Ikeda, Hiroaki.

Proceedings - Electronic Components and Technology Conference. 2012. p. 673-677 6248904.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Takatani, H, Tanaka, Y, Oizono, Y, Nabeshima, Y, Okumura, T, Sudo, T, Sakai, A, Uchiyama, S & Ikeda, H 2012, PDN impedance and noise simulation of 3D SiP with a widebus structure. in Proceedings - Electronic Components and Technology Conference., 6248904, pp. 673-677, 2012 IEEE 62nd Electronic Components and Technology Conference, ECTC 2012, San Diego, CA, 12/5/29. https://doi.org/10.1109/ECTC.2012.6248904
Takatani H, Tanaka Y, Oizono Y, Nabeshima Y, Okumura T, Sudo T et al. PDN impedance and noise simulation of 3D SiP with a widebus structure. In Proceedings - Electronic Components and Technology Conference. 2012. p. 673-677. 6248904 https://doi.org/10.1109/ECTC.2012.6248904
Takatani, Hiroki ; Tanaka, Yosuke ; Oizono, Yoshiaki ; Nabeshima, Yoshitaka ; Okumura, Takafumi ; Sudo, Toshio ; Sakai, Atsushi ; Uchiyama, Shiro ; Ikeda, Hiroaki. / PDN impedance and noise simulation of 3D SiP with a widebus structure. Proceedings - Electronic Components and Technology Conference. 2012. pp. 673-677
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