PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure

Yoshiaki Oizono, Yoshitaka Nabeshima, Takafumi Okumura, Toshio Sudo, Atsushi Sakai, Shiro Uchiyama, Hiroaki Ikeda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Power supply impedance and simultaneous switching output (SSO) noise for a 3D system-in-package (SiP) with a wide bus structure have been investigated. The 3D SiP consisted of 3 stacked chips and an organic package substrate. These three chips were a memory chip on the top, Si interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. Next, these 3 stacked chips were assembled on the organic package substrate, whose size was 26 mm by 26 mm. The 3D stacked SiP with a widebus structure was estimated to have large SSO noise compared with conventional memory devices with small number of I/O s. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.). Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.

Original languageEnglish
Title of host publication2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOIs
Publication statusPublished - 2011
Event2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka
Duration: 2012 Jan 312012 Feb 2

Other

Other2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
CityOsaka
Period12/1/3112/2/2

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Substrates
Data storage equipment
Silicon
System-in-package

ASJC Scopus subject areas

  • Control and Systems Engineering

Cite this

Oizono, Y., Nabeshima, Y., Okumura, T., Sudo, T., Sakai, A., Uchiyama, S., & Ikeda, H. (2011). PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure. In 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 [6263028] https://doi.org/10.1109/3DIC.2012.6263028

PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure. / Oizono, Yoshiaki; Nabeshima, Yoshitaka; Okumura, Takafumi; Sudo, Toshio; Sakai, Atsushi; Uchiyama, Shiro; Ikeda, Hiroaki.

2011 IEEE International 3D Systems Integration Conference, 3DIC 2011. 2011. 6263028.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Oizono, Y, Nabeshima, Y, Okumura, T, Sudo, T, Sakai, A, Uchiyama, S & Ikeda, H 2011, PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure. in 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011., 6263028, 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011, Osaka, 12/1/31. https://doi.org/10.1109/3DIC.2012.6263028
Oizono Y, Nabeshima Y, Okumura T, Sudo T, Sakai A, Uchiyama S et al. PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure. In 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011. 2011. 6263028 https://doi.org/10.1109/3DIC.2012.6263028
Oizono, Yoshiaki ; Nabeshima, Yoshitaka ; Okumura, Takafumi ; Sudo, Toshio ; Sakai, Atsushi ; Uchiyama, Shiro ; Ikeda, Hiroaki. / PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure. 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011. 2011.
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