PDN impedance modeling of 3D system-in-package

Yoshiaki Oizono, Yoshitaka Nabeshima, Takafumi Okumura, Toshio Sudo, Atsushi Sakai, Hiroaki Ikeda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Power supply impedance of power distribution network (PDN) for a 3D system-in-package (SiP) has been investigated. The 3D SiP consisted of 3 stacked chips and an organic package substrate. These three chips were a memory chip on the top, Si interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. A large number of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. Next, the 3 stacked chips were assembled on the organic package substrate, whose size was 26 mm by 26 mm. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.). Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized. In this paper, the PDN impedances of the memory chip, Si interposer, and the logic chip were calculated respectively, and then the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.

Original languageEnglish
Title of host publication2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
DOIs
Publication statusPublished - 2011
Event2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011 - Hanzhou
Duration: 2011 Dec 122011 Dec 14

Other

Other2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
CityHanzhou
Period11/12/1211/12/14

Fingerprint

Electric power distribution
Substrates
Data storage equipment
Silicon
System-in-package

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Oizono, Y., Nabeshima, Y., Okumura, T., Sudo, T., Sakai, A., & Ikeda, H. (2011). PDN impedance modeling of 3D system-in-package. In 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011 [6213751] https://doi.org/10.1109/EDAPS.2011.6213751

PDN impedance modeling of 3D system-in-package. / Oizono, Yoshiaki; Nabeshima, Yoshitaka; Okumura, Takafumi; Sudo, Toshio; Sakai, Atsushi; Ikeda, Hiroaki.

2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011. 2011. 6213751.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Oizono, Y, Nabeshima, Y, Okumura, T, Sudo, T, Sakai, A & Ikeda, H 2011, PDN impedance modeling of 3D system-in-package. in 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011., 6213751, 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011, Hanzhou, 11/12/12. https://doi.org/10.1109/EDAPS.2011.6213751
Oizono Y, Nabeshima Y, Okumura T, Sudo T, Sakai A, Ikeda H. PDN impedance modeling of 3D system-in-package. In 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011. 2011. 6213751 https://doi.org/10.1109/EDAPS.2011.6213751
Oizono, Yoshiaki ; Nabeshima, Yoshitaka ; Okumura, Takafumi ; Sudo, Toshio ; Sakai, Atsushi ; Ikeda, Hiroaki. / PDN impedance modeling of 3D system-in-package. 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011. 2011.
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