Physical mechanism of buffer-related lag and current collapse in GaN-based FETs and their reduction by introducing a field plate

Atsushi Nakajima, Keiichi Itagaki, Kazushige Horio

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Two-dimensional transient analysis of field-plate AlGaN/GaN HEMTs and GaN MESFETs is performed, considering a deep donor and a deep acceptor in the semi-insulating GaN buffer layer. Quasi-pulsed I-V curves are derived from the transient characteristics. It is studied how the existence of a field plate affects buffer-related drain lag, gate lag and current collapse. It is shown that in both FETs, the drain lag is reduced by introducing a field plate, because electron injection into the buffer layer is weakened by it, and trapping effects are reduced. It is also shown that the buffer-related current collapse and gate lag are reduced in the field-plate structures. The dependence on SiN passivation layer thickness under the field plate is also studied, suggesting that there is an optimum thickness of the SiN layer to minimize buffer-related current collapse and drain lag in GaN HEMTs and MESFETs.

Original languageEnglish
Title of host publicationIEEE International Reliability Physics Symposium Proceedings
Pages722-726
Number of pages5
DOIs
Publication statusPublished - 2009
Event2009 IEEE International Reliability Physics Symposium, IRPS 2009 - Montreal, QC
Duration: 2009 Apr 262009 Apr 30

Other

Other2009 IEEE International Reliability Physics Symposium, IRPS 2009
CityMontreal, QC
Period09/4/2609/4/30

Fingerprint

High electron mobility transistors
Buffer layers
Field effect transistors
Electron injection
Passivation
Transient analysis

Keywords

  • Current collapse
  • Device simulation
  • Field plate
  • GaN
  • HEMT
  • Trap

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Nakajima, A., Itagaki, K., & Horio, K. (2009). Physical mechanism of buffer-related lag and current collapse in GaN-based FETs and their reduction by introducing a field plate. In IEEE International Reliability Physics Symposium Proceedings (pp. 722-726). [5173337] https://doi.org/10.1109/IRPS.2009.5173337

Physical mechanism of buffer-related lag and current collapse in GaN-based FETs and their reduction by introducing a field plate. / Nakajima, Atsushi; Itagaki, Keiichi; Horio, Kazushige.

IEEE International Reliability Physics Symposium Proceedings. 2009. p. 722-726 5173337.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nakajima, A, Itagaki, K & Horio, K 2009, Physical mechanism of buffer-related lag and current collapse in GaN-based FETs and their reduction by introducing a field plate. in IEEE International Reliability Physics Symposium Proceedings., 5173337, pp. 722-726, 2009 IEEE International Reliability Physics Symposium, IRPS 2009, Montreal, QC, 09/4/26. https://doi.org/10.1109/IRPS.2009.5173337
Nakajima, Atsushi ; Itagaki, Keiichi ; Horio, Kazushige. / Physical mechanism of buffer-related lag and current collapse in GaN-based FETs and their reduction by introducing a field plate. IEEE International Reliability Physics Symposium Proceedings. 2009. pp. 722-726
@inproceedings{bfc861f8158c4736b4579ab64a3f6540,
title = "Physical mechanism of buffer-related lag and current collapse in GaN-based FETs and their reduction by introducing a field plate",
abstract = "Two-dimensional transient analysis of field-plate AlGaN/GaN HEMTs and GaN MESFETs is performed, considering a deep donor and a deep acceptor in the semi-insulating GaN buffer layer. Quasi-pulsed I-V curves are derived from the transient characteristics. It is studied how the existence of a field plate affects buffer-related drain lag, gate lag and current collapse. It is shown that in both FETs, the drain lag is reduced by introducing a field plate, because electron injection into the buffer layer is weakened by it, and trapping effects are reduced. It is also shown that the buffer-related current collapse and gate lag are reduced in the field-plate structures. The dependence on SiN passivation layer thickness under the field plate is also studied, suggesting that there is an optimum thickness of the SiN layer to minimize buffer-related current collapse and drain lag in GaN HEMTs and MESFETs.",
keywords = "Current collapse, Device simulation, Field plate, GaN, HEMT, Trap",
author = "Atsushi Nakajima and Keiichi Itagaki and Kazushige Horio",
year = "2009",
doi = "10.1109/IRPS.2009.5173337",
language = "English",
isbn = "0780388038",
pages = "722--726",
booktitle = "IEEE International Reliability Physics Symposium Proceedings",

}

TY - GEN

T1 - Physical mechanism of buffer-related lag and current collapse in GaN-based FETs and their reduction by introducing a field plate

AU - Nakajima, Atsushi

AU - Itagaki, Keiichi

AU - Horio, Kazushige

PY - 2009

Y1 - 2009

N2 - Two-dimensional transient analysis of field-plate AlGaN/GaN HEMTs and GaN MESFETs is performed, considering a deep donor and a deep acceptor in the semi-insulating GaN buffer layer. Quasi-pulsed I-V curves are derived from the transient characteristics. It is studied how the existence of a field plate affects buffer-related drain lag, gate lag and current collapse. It is shown that in both FETs, the drain lag is reduced by introducing a field plate, because electron injection into the buffer layer is weakened by it, and trapping effects are reduced. It is also shown that the buffer-related current collapse and gate lag are reduced in the field-plate structures. The dependence on SiN passivation layer thickness under the field plate is also studied, suggesting that there is an optimum thickness of the SiN layer to minimize buffer-related current collapse and drain lag in GaN HEMTs and MESFETs.

AB - Two-dimensional transient analysis of field-plate AlGaN/GaN HEMTs and GaN MESFETs is performed, considering a deep donor and a deep acceptor in the semi-insulating GaN buffer layer. Quasi-pulsed I-V curves are derived from the transient characteristics. It is studied how the existence of a field plate affects buffer-related drain lag, gate lag and current collapse. It is shown that in both FETs, the drain lag is reduced by introducing a field plate, because electron injection into the buffer layer is weakened by it, and trapping effects are reduced. It is also shown that the buffer-related current collapse and gate lag are reduced in the field-plate structures. The dependence on SiN passivation layer thickness under the field plate is also studied, suggesting that there is an optimum thickness of the SiN layer to minimize buffer-related current collapse and drain lag in GaN HEMTs and MESFETs.

KW - Current collapse

KW - Device simulation

KW - Field plate

KW - GaN

KW - HEMT

KW - Trap

UR - http://www.scopus.com/inward/record.url?scp=70449102621&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70449102621&partnerID=8YFLogxK

U2 - 10.1109/IRPS.2009.5173337

DO - 10.1109/IRPS.2009.5173337

M3 - Conference contribution

AN - SCOPUS:70449102621

SN - 0780388038

SN - 9780780388031

SP - 722

EP - 726

BT - IEEE International Reliability Physics Symposium Proceedings

ER -