Power gating for FDSOI using dynamically body-biased power switch

Yuichi Kumagai, Masaru Kudo, Kimiyoshi Usami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose a Dynamically Biased Multi Threshold CMOS (DBMT) technique for power gating in FDSOI. In DBMT, effective threshold voltage of a high-Vt power switch transistor is lowered by forward body biasing (FBB) to improve performance at the operation, while it is raised by reverse body biasing (RBB) to further reduce leakage in the sleep state. We applied this technique to a 32-bit multiplier circuit of an experimental CPU Geyser-1 in which the multiplier is power gated at run time in a fine-grained manner during the CPU operation [1]. Simulated results in 65nm FDSOI with thin BOX revealed that the area of the power switch (PS) in DBMT technique can be reduced by 55% as compared to the conventional MTCMOS when suppressing the delay increase due to PS insertion within 10%. DBMT reduces leakage energy of the multiplier considering the energy overhead by up to 55% as compared to the MTCMOS when running application programs.

Original languageEnglish
Title of host publicationEUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages221-224
Number of pages4
ISBN (Print)9781479969111
DOIs
Publication statusPublished - 2015 Mar 18
Event2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015 - Bologna, Italy
Duration: 2015 Jan 262015 Jan 28

Other

Other2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015
CountryItaly
CityBologna
Period15/1/2615/1/28

Keywords

  • Body-Bias
  • Low Power Technique
  • Power Gating
  • Sillicon-on-Thin-BOX MOSFET

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Kumagai, Y., Kudo, M., & Usami, K. (2015). Power gating for FDSOI using dynamically body-biased power switch. In EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (pp. 221-224). [7063813] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ULIS.2015.7063813