Power integrity behavior for various packaging environments

Masahiro Terasaki, Sho Kiyosige, Wataru Ichimura, Ryota Kobayashi, Genki Kubo, Hiroki Otsuka, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Power integrity design has become a critical issue in digital electronic systems, as advanced CMOS LSIs operate at higher clock frequency and at lower supply voltage. Power supply fluctuation excited by core circuits or I/O buffer circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be taking into consideration in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN created by the parallel combination of on-chip capacitance and package inductance induce the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed on-chip PDN properties. The measurement and analysis of power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions the critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip. Furthermore QFP and BGA are used for a package and the effect of anti-resonance and power supply noise control by the total impedance of a chip package board are verified from the difference in inductance.

Original languageEnglish
Title of host publicationICSJ 2013 - IEEE CPMT Symposium Japan
PublisherIEEE Computer Society
DOIs
Publication statusPublished - 2013
Event2013 3rd IEEE CPMT Symposium Japan, ICSJ 2013 - Kyoto
Duration: 2013 Nov 112013 Nov 13

Other

Other2013 3rd IEEE CPMT Symposium Japan, ICSJ 2013
CityKyoto
Period13/11/1113/11/13

Fingerprint

Electric power distribution
Packaging
Inductance
Networks (circuits)
Buffer circuits
Damping
Acoustic impedance
Acoustic variables control
Signal interference
Electromagnetic waves
Clocks
Capacitance
Degradation
Electric potential

Keywords

  • Anti-resonance peak
  • co-design
  • Power integrity
  • total PDN impedance

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Terasaki, M., Kiyosige, S., Ichimura, W., Kobayashi, R., Kubo, G., Otsuka, H., & Sudo, T. (2013). Power integrity behavior for various packaging environments. In ICSJ 2013 - IEEE CPMT Symposium Japan [6756112] IEEE Computer Society. https://doi.org/10.1109/ICSJ.2013.6756112

Power integrity behavior for various packaging environments. / Terasaki, Masahiro; Kiyosige, Sho; Ichimura, Wataru; Kobayashi, Ryota; Kubo, Genki; Otsuka, Hiroki; Sudo, Toshio.

ICSJ 2013 - IEEE CPMT Symposium Japan. IEEE Computer Society, 2013. 6756112.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Terasaki, M, Kiyosige, S, Ichimura, W, Kobayashi, R, Kubo, G, Otsuka, H & Sudo, T 2013, Power integrity behavior for various packaging environments. in ICSJ 2013 - IEEE CPMT Symposium Japan., 6756112, IEEE Computer Society, 2013 3rd IEEE CPMT Symposium Japan, ICSJ 2013, Kyoto, 13/11/11. https://doi.org/10.1109/ICSJ.2013.6756112
Terasaki M, Kiyosige S, Ichimura W, Kobayashi R, Kubo G, Otsuka H et al. Power integrity behavior for various packaging environments. In ICSJ 2013 - IEEE CPMT Symposium Japan. IEEE Computer Society. 2013. 6756112 https://doi.org/10.1109/ICSJ.2013.6756112
Terasaki, Masahiro ; Kiyosige, Sho ; Ichimura, Wataru ; Kobayashi, Ryota ; Kubo, Genki ; Otsuka, Hiroki ; Sudo, Toshio. / Power integrity behavior for various packaging environments. ICSJ 2013 - IEEE CPMT Symposium Japan. IEEE Computer Society, 2013.
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