Power integrity improvement by controlling on-die PDN properties

Toshio Sudo, Sho Kiyoshige, Wataru Ichimura, Masahiro Terasaki, Ryota Kobayashi, Genki Kubo, Hiroki Otsuka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Power integrity has became a serious issue in the advanced CMOS digital systems, because power supply noise must be suppressed to guarantee normal logic operation and its stability. Therefore, chip-package-board co-design has become important by taking into consideration the total impedance seen from the chip. Especially, parallel resonance peaks in the power distribution network (PDN) due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, three test chips were designed with different on-chip PDN properties. The effects of critical damping condition for the total PDN impedance on power supply noise has been examined by adding different RC circuit to the intrinsic on-die RC circuit of chip. The measurement and analysis of power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.

Original languageEnglish
Title of host publicationEDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
Pages44-47
Number of pages4
DOIs
Publication statusPublished - 2013
Event2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013 - Nara
Duration: 2013 Dec 122013 Dec 15

Other

Other2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013
CityNara
Period13/12/1213/12/15

Fingerprint

Electric power distribution
Damping
Networks (circuits)
Signal interference
Electric power systems
Degradation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Sudo, T., Kiyoshige, S., Ichimura, W., Terasaki, M., Kobayashi, R., Kubo, G., & Otsuka, H. (2013). Power integrity improvement by controlling on-die PDN properties. In EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (pp. 44-47). [6724453] https://doi.org/10.1109/EDAPS.2013.6724453

Power integrity improvement by controlling on-die PDN properties. / Sudo, Toshio; Kiyoshige, Sho; Ichimura, Wataru; Terasaki, Masahiro; Kobayashi, Ryota; Kubo, Genki; Otsuka, Hiroki.

EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium. 2013. p. 44-47 6724453.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sudo, T, Kiyoshige, S, Ichimura, W, Terasaki, M, Kobayashi, R, Kubo, G & Otsuka, H 2013, Power integrity improvement by controlling on-die PDN properties. in EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium., 6724453, pp. 44-47, 2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013, Nara, 13/12/12. https://doi.org/10.1109/EDAPS.2013.6724453
Sudo T, Kiyoshige S, Ichimura W, Terasaki M, Kobayashi R, Kubo G et al. Power integrity improvement by controlling on-die PDN properties. In EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium. 2013. p. 44-47. 6724453 https://doi.org/10.1109/EDAPS.2013.6724453
Sudo, Toshio ; Kiyoshige, Sho ; Ichimura, Wataru ; Terasaki, Masahiro ; Kobayashi, Ryota ; Kubo, Genki ; Otsuka, Hiroki. / Power integrity improvement by controlling on-die PDN properties. EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium. 2013. pp. 44-47
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