Power Reduction Technique for Dynamic Reconfigurable Processors with Dynamic Assignment of Dual Supply Voltages

Y. Umahashi, Y. Kambayashi, M. Kato, Y. Hasegawa, H. Amano, K. Usami

Research output: Contribution to journalArticle

Original languageEnglish
Pages (from-to)213-216
JournalThe 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08)
Publication statusPublished - 2008 Jul 8

Cite this

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title = "Power Reduction Technique for Dynamic Reconfigurable Processors with Dynamic Assignment of Dual Supply Voltages",
author = "Y. Umahashi and Y. Kambayashi and M. Kato and Y. Hasegawa and H. Amano and K. Usami",
year = "2008",
month = "7",
day = "8",
language = "English",
pages = "213--216",
journal = "The 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08)",

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T1 - Power Reduction Technique for Dynamic Reconfigurable Processors with Dynamic Assignment of Dual Supply Voltages

AU - Umahashi, Y.

AU - Kambayashi, Y.

AU - Kato, M.

AU - Hasegawa, Y.

AU - Amano, H.

AU - Usami, K.

PY - 2008/7/8

Y1 - 2008/7/8

M3 - Article

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EP - 216

JO - The 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08)

JF - The 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08)

ER -